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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (108710)	4/30/2000 11:24:00 PM
From: Joe NYC	Read Replies (2) \| Respond to of 1571813

Dan, I hope someone who is an EE will step in and liberate us from embarsing ourselves more by speculating how the bus operates, but anyway, here is my theory: You have a clock that generates a signal: _ \| \|_ 1234 Now, the CPU has the data lines, that are basically just connections to the outside world that can be at high or low voltage. Suppose you are trying to communicate data string 1011. The voltage on the data line would be _ __ _ 1234 So the CPU reads the voltage on the data lines 4 times in the cycle and that's how it get's the data. I am not sure if the concept of frequency really applies on the data lines. Suppose you have a string to all zeros. The lines would be low all the time. If you had 10101010, it would in fact look like a sine wave at twice the frequency. Joe

To: Dan3 who wrote (108710)	4/30/2000 11:27:00 PM
From: Bilow	Read Replies (1) \| Respond to of 1571813

Hi Dan3; Re "Quad" pumped bus &c... I don't know what Intel means with this, but in the SRAM area, "QDR" or "Quad Data Rate" actually means separated DIN and DOUT buses, with DDR on each bus. This means that the design does offer 4x the rate of the usual bus width, but they use twice the pins. This would be in keeping with your assumption. On the other hand, with the use of PLLs or DLLs, a true quad data rate is possible, and really isn't a terribly bad idea. I would rather limit myself to DDR, as the frequencies you generate with that are no worse than the ones you generate with QDR, but it has been very popular recently to design with a slow system clock that every board or chip converts to a higher frequency. This reduces the frequency of your system clock. A lot of PLL chips allow this. If the PLL chips were set for 2x clock multiplication, then you would have a DDR system. But if they happened to be set for 4x, then you would have a QDR system. -- Carl P.S. I now see that I am supposed to include some wave forms... Quad data rate system: SysClk /-------\_______/-------\_______/-------\_______/ PllClk /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ DataBus[] 0 \| 1 \| 2 \| 3 \| 4 \| 5 \| 6 \| 7 \| 8 \| 9 \| A \| B \| B Only SysClk and DataBus[] need exist outside the chip. PllClk could be a signal internal to the ICs only.