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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: richard surckla who wrote (43145)	5/29/2000 5:34:00 PM
From: Dan3	Read Replies (2) \| Respond to of 93625

Re: One would really have to be stupid to believe anything in any article written about Rambus or Intel from Tom's Hardware where they have made an open admission to hating Rambus and Intel. Tom doesn't like Rambus because, right or wrong, he thinks it's a fraud. He's a journalist of sorts, and "wins" if he can expose the truth before others figure it out. Samsung is the leading producer of rambus chips, it "wins" if it can convince people to pay a lot of money for the chips it produces. You might want to reconsider your conclusion that samsung is impartial and Tom isn't. Dan

To: richard surckla who wrote (43145)	5/29/2000 6:31:00 PM
From: Bilow	Respond to of 93625

Re Samsung and RDRAM... From Samsung's recent 512Mb DDR DRAM chip announcement: Samsung uevelops[sic] World First 512Mb DRAM Samsung's 512Mb DRAM can support both synchronous data rate DRAM and double data rate SDRAM specifications. samsung.com Another quote: "The 512Mb DRAM uses the same packaging as 256Mb DRAMs, simplifying memory upgrades." This is in contrast to the 256Mb RDRAM which uses a different package from the 128Mb RDRAM. (See #reply-13593644 ) Also note that there is no 512Mb RDRAM. The largest RDRAM was announced a few months ago in this Samsung PR: samsung.com Another quote: "The world market for this device is expected to reach annual sales of US$41.1 billion by 2004." At say, $25 per chip, this market size would be $41.1 billion / $25 = 1.6 billion per year, or 137 million per month. Doesn't look like Samsung thinks that RDRAM is going to supplant DDR and SDRAM any time in the next 4 years. DDR-2 will be around before then. Another quote: "The high-end memory market is forecast to consist of DDR devices for server PCs and Rambus DRAM devices for workstations. The general PC market will center on three main products: SDR DRAMs, DDR SDRAMs and Rambus DRAMs. Samsung Electronics is capable of mass-producing all three of these types, so the company's market dominance is expected to accelerate." This is the strongest call for RDRAM that Samsung has put out recently, and it is pretty weak. A last quote: "The 512Mb DRAM uses a chip design that can support either the synchronous mode of the current PC-100 and PC-133, or the next-generation DDR (double data rate) memory specifications. This design will enable better production line flexibility, quickening Samsung's response time to market demands." This is another mention of the flexibility that exists between DDR and SDRAM manufacturing. -- Carl

To: richard surckla who wrote (43145)	5/29/2000 6:47:00 PM
From: Bilow	Respond to of 93625

Re believing Tom's or Samsung. Another Samsung white paper, one a lot more recent than their RDRAM white paper: Double Data Rate SGRAM Delivers Needed Bandwidth for 3-D Graphics Graphics chipset vendors are always the first to jump on a new, faster DRAM. They were the first to use EDO and the first to use SDRAM. They'll be the first to use DDR. ... It assures boost in performance with a little premium over the SDRAM. ... The continuous improvement in DDR SGRAM technology gives longevity to the system design with multiple generations (higher density and advanced die shrink) and ultra high-speed operation (DDR-II, more bandwidth). ... In Figure 2, we would also like to share our view of the graphics memory transition history and future graphics memory demand forecast data with our customers. usa.samsungsemi.com Samsung now has engineering samples available for DDR SDRAM DIMMs: usa.samsungsemi.com Samsung supports a DDR interface in their standard cell. Where's the RAC interface?: IO IP available - PCI((33MHz, 66MHz, 3.3V), (33MHz, 3.3/5V tolerant)) - USB(Full speed/Low speed, 12/1.5 MHz) - SSTL2(DDR SDRAM Interface, up to 200MHz) - AGP(3.3V 1X/2X, 1.5V 2X/4X, 66MHz@1X,133MHz@2X, 266MHz@4X) - PECL(2.5V Interface, up to 400MHz) - HSTL(class1, class2, 30MHz) - LVDS(3.3V(2.5V optional) interface, 300MHz) intl.samsungsemi.com I'm not entirely certain as to the validity of the following link, but it seems to show Samsung with DDR DIMM modules at 4x the density of RIMM modules: intl.samsungsemi.com -- Carl P.S. Any Korean speakers know what this is all about? "DDR 2000": 210.121.148.40

To: richard surckla who wrote (43145)	5/29/2000 8:46:00 PM
From: jim kelley	Read Replies (3) \| Respond to of 93625

Richard, Re: Tom's Biased Tests QMC and the other "memory latency tests" cynically designed by Tom's boy are selected and designed to exploit the "initial latency" penalty of RDRAM. They are trying to fool "mom" and "pop" as BILOW says. RDRAM has slightly higher "intitial latency" and much lower "average latency" than SDRAM or DDR DRAM. The use of "random data accesses" to main memory as the dominant form of access penalizes RDRAM and is in fact unrealistic. It means that essentially every access is made into a different RDRAM page and that that page has to be enabled and the initial penalty is always incurred. Most applications programs have both "program and data locality". It appears that some of Tom's programs are a small enough set of instructions to be contained entirely in the cache and the data to be referenced is randomly scattered throughout memory. Further, "cache memory" would not work at all if both program and data were randomly scattered through main memory. This explains in part why the programs sometimes mysteriously work better when the cache is turned off. Typically, a instruction cache miss will produce a 64 bit read. That is four 16 bit read operations to a single channel RDRAM. Thus, ordinarily we will obtain a latency that is the average of the four memory reads from contiguous page locations. ARRAY operations can be efficiently performed with RDRAM memory in a way which will result in much higher performance than corresponding optimized SDRAM operations by arranging the array elements in memory in such a way as to take advantage of the much lower average latency. Essentially, what Tom has done here is heavily eight the benchmark tests to highlight the known initial latency penalty. He uses this "initial latency" penalty to wipe out the bandwidth advantage that RDRAM has over SDRAM with normal programs. So what Tom has done is cynically repeal the laws of "program locality" and "data locality" which have guided the develop of computer memory architectures for the last 30 years. He has no shame and a firm belief in the ignorance of the masses. It just keeps getting better all the time!