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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: jim kelley who wrote (43172)	5/30/2000 3:37:00 AM
From: Joe NYC	Read Replies (1) \| Respond to of 93625

jim kelley, Actually the post is my own, I do not copy without attribution. I have to say that I was impressed with that post as well. It doesn't mean that I agreed with it, but you argued your position reasonably, and provided a reasonable basis for your assumptions. I think richard surckla and misheldo(sp?) are now strongly challenging you for the position of Ringo Starr of the Rambus thread. The "64 bit cache line access" I think the cache line is 32 bytes in P6 and 64 bytes in K7 Of course, the design of Tom's benchmark programs was focused on stressing "initial latency." That particular test was even called MemLatency. Transferring chunks of data, or reading and writing sequentially is a bandwidth test. He has those as well. Programs have a great deal of locality. True, but the CPU's have large L2 caches these days, and when there is access of data or program with good locality, it goes from the cache. The main memory will not even know it happened. What the memory will see is accesses of data that don't conform with this locality, meaning they are not it L1 or L2. This means there is great fear of RDRAM at AMD. Pointing out weaknesses of Rambus before they are obvious to everyone is actually a disservice to AMD. If Rambus is in fact a dead end street, it would serve AMD very well if Intel went a lot further into this dead end street. Joe