IP reuse called essential to advanced chip designs
By Peggy Aycinena
Integrated Systems Design
(06/06/00, 8:17 p.m. EST)
LOS ANGELES ? The design gap will become a reality unless new methodologies involving design reuse are put into play, said Theo Claasen of Philips Semiconductors in a keynote address at the Design Automation Conference on Tuesday (June 6). Claasen, executive vice president and chief technology officer for Philips Semiconductor (Eindhoven, Netherlands), suggested strategies that he said will guarantee increases in design reuse needed for today's deep-submicron process technologies and system-on-a-chip designs.
Worldwide demand for portable communication devices and entertainment systems, combined with dramatic increases in device integration, require a different design mind set than the earlier era's, when the PC market was the principal driver for semiconductor design, Claasen said.
The current design crisis is nothing new, Claasen said. As process geometries shrink and on-chip integration increases, design methodologies haven't actually fallen behind, but have improved in fits and starts along the way. This design gap between available semiconductor technologies and their implementation in chip designs is more like a design lag, Claasen said, but that situation is about to change.
Mainline mandate
Consumer demand for small, dense, low-power designs will depend completely on intellectual property (IP) reuse if today's brutal time-to-market pressures are to be met, Claasen said. Design reuse must become mainline ? complete with standards and guidelines, comprehensive libraries of reusable elements, appropriate development tools, and rapid silicon prototyping ? to prevent the design gap from becoming a full-blown design crisis, the keynoter said.
Claasen laid out the four generations of IP. The first generation consisted of standard cell reuse, which is now well understood and utilized. The second generation consists of IP block reuse. Although intuitively pleasing, this generation currently includes only memories, CPU and DSP cores, and some peripheral devices. It does not include the plethora of unique cores that are currently available but which suffer from inadequate characterization, anonymity within a company, or the search for a wider market. Claasen cited recent efforts by the VSI Alliance on standards and guidelines as the type of work that is required to fully realize the potential of second-generation IP.
As an aside, Claasen noted that only one or two companies dominate the history of the PC industry. They managed to establish and maintain de facto standards that clearly enhanced progress in the PC product space. (Claasen got a big laugh when he noted that the U.S. government has not been similarly impressed by the benefits of one company's dominance of the PC platform market.)
But in the IP space, disparate consumer products that span the video, audio, and telecommunication markets will not allow de facto standards to be set by one or two companies, Claasen said. Application-specific platforms will emerge that will each need to be uniquely characterized by computational speed, power requirements, real-time versus non-real-time system constraints, form factor, and cost.
Therefore, the third generation of IP now emerging is architectural, according to Claasen. Philips Semiconductors is now using such a flexible platform, he said. In addition, rapid silicon prototyping will be crucial to validating the architectural IP at a pace required by time-to-market demands, he said.
Finally, Claasen called "IC reuse" the fourth and ultimate generation of IP reuse. When the industry is working to achieve 100-million-plus transistor chips and masks have grown prohibitively expensive, it will be impossible to synthesize silicon if any possibility lingers of design error, specification error, or manufacturing variations. Therefore, silicon efficiency will mandate compiler and computational efficiency, reconfigurable interconnects, and on-board software, which in turn will open the way for complete IC reuse, according to Claasen.
Claasen concluded by stating that design efficiency is in danger of not keeping pace with Moore's Law and process technologies. The next generation of reuse technologies will be dependent on solutions that . And IP reuse is coming of age as architectural reuse emerges as a reality, he said.
The final word in IP reuse will involve IC reuse and retargetable architectures ? a technology that may never come to pass, Claasen said.
Management has an obligation to pursue, encourage, and demand the application of all generations of IP reuse, Claasen said. This philosophy will be mandatory for IC design going forward, he said.
Peggy Aycinena is Editor of ISD Magazine, a sister publication of EE Times.
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