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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: kapkan4u who wrote (114925)	6/7/2000 11:49:00 PM
From: milo_morai	Read Replies (1) \| Respond to of 1571757

Kap what did you think about the T-bird launch? Do you think mustang will have a wider data path to L2 than 64 bits?

To: kapkan4u who wrote (114925)	6/8/2000 12:43:00 PM
From: Pravin Kamdar	Read Replies (2) \| Respond to of 1571757

Kap, I have been saying for a while that Willy's double-clocked ALUs will not scale. I also proposed this as an issue from the get-go. It just seems to be common sense that it would be a problem. Also, what do you, Scumbria, and Pete (and others) think about the performance increase that we should expect by going to a synchronous memory system where the FSB and main memory are both clocked at 266 Mhz? Will Intel have asynchronous solutions with their DDR chipsets? Thanks, Pravin.

To: kapkan4u who wrote (114925)	6/8/2000 2:00:00 PM
From: EricRR	Read Replies (2) \| Respond to of 1571757

I found this old post from Tench: Message 13030478 And Willamette's FPU will not run faster than 700 MHz. Tenchusatsu Was he joking? Does Willy's FPU really run at half clock speed? (I thought it was only SSE and MMX) Also I thought that Willy had a unified integer/FPU decoding pipeline. How can the FPU run at a different speed than the integer if they use the same decoding pipeline? Also can anyone guess as to what effect the trace cache architecture would have on the performance of server type applications? Would it make L2 cache hits slower?