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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Joe NYC who wrote (115694)6/13/2000 2:58:00 AM
From: Pravin Kamdar  Read Replies (3) | Respond to of 1572209
 
For those of you who have not looked at this comparison on JCs, it is worth a look:

jc-news.com

Pravin.
PS: Time to take some Pepcid and hit the sack. I picked up a bunch (and I mean a bunch) of Citrix today at $22. Keeping my fingers crossed for a bounce by Friday.



To: Joe NYC who wrote (115694)6/13/2000 3:08:00 AM
From: Scumbria  Respond to of 1572209
 
Joe,

I think the few clocks of latency are going to be very important as the CPU speed go up, and a few clocks of latency of the FSB will translate to several dozen (CPU) clocks of stalled CPU.

That is true. As the ratio of core clocks to bus clocks increases, the penalty for synchronizing off chip increases.

Scumbria



To: Joe NYC who wrote (115694)6/13/2000 3:15:00 AM
From: Scumbria  Read Replies (1) | Respond to of 1572209
 
Joe,

you could think of scheme where the critical word is fed to the CPU (2 bytes at the time) and once there, the CPU could continue to run, even before full 8 bytes are retrieved (as is the case with off chip north bridge)

It is standard for most memory subsystems to deliver critical word first, to allow the instruction stream to continue as quickly as possible.

Scumbria