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To: Dan3 who wrote (46837)	7/12/2000 2:17:30 PM
From: Dave B	Read Replies (2) \| Respond to of 93625

Dan, Willamette will have an internal bus at least as wide as Coppermine. That's why the volume chipset for Willamette (Tulloch) isn't going to be stuck with Rambus. An Intel engineer told me 5 or 6 weeks ago that Tulloch was a cost-reduced version of Tehama and obviously would be RDRAM-based. They weren't sure yet whether or not it would be single or dual RDRAM channel (which affected the number of layers in the board), but it was definitely RDRAM-based. That information was based on a roadmap presentation he saw in late May. Do you have some announcement that says that they've changed it to SDRAM (or anything else)? Please point me to a link or copy of the announcement, if so. Dave

To: Dan3 who wrote (46837)	7/12/2000 4:37:50 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 93625

Dan, <Do you realize that, internally, coppermine has a 128 bit wide connection between the core and the cache? Dual DDR would be a perfect match for Coppermine.> First of all, Coppermine has a 256-bit wide connection between the core and L2 cache. Second, AMD's Thunderbird only has a 64-bit wide connection between core and L2. Would you conclude that T-bird needs dual-DDR less than Coppermine? I wouldn't. Finally, the width of the L2 connection really has nothing to do with the width of the DRAM channel. As long as the DRAM channel can provide the necessary amount of bandwidth without impacting latency too much, the width of the DRAM channel doesn't matter. I don't know why you're saying otherwise. <Willamette will have an internal bus at least as wide as Coppermine. That's why the volume chipset for Willamette (Tulloch) isn't going to be stuck with Rambus.> How do you know both of these "facts"? And once again, why should the width of Willamette's internal bus matter? Tenchusatsu