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To: chic_hearne who wrote (675)7/13/2000 12:20:19 PM
From: GoutamRead Replies (1) | Respond to of 275872
 
Chic,

Very interesting stuff from your company - IBM unveils 2GHz Embedded SRAM Hope AMD will be able to get this technology on their chip to reduce existing latencies with their on-chip L1 and L2 caches.

IBM credits its CMOS and Copper processes for this achievement. They also say that low-k dielectric may allow them to make further improvements. Since AMD is an adoptee of both techniques, AMD may benefit from this.

ebnews.com ______________________

Some interesting excerpts from the above article:

[...]
IBM Corp. said it has combined line-width circuitry shrinks achieved through 0.18-micron processes, its new CMOS technology, and the low resistance of copper interconnects to develop a 2-GHz embedded SRAM device.
[...]
The new design speeds access to machine instructions in the Level 1 cache to more than 2 GHz at 34 Kbits with a read access time of less than 430 ps, according to the company.
[...]
"With this new [technology], the CPU doesn't have to wait for its relatively slow memory to access data," Joshi said. "Currently reported cache SRAMs function well below 1 GHz, with access delays above 600 picoseconds."
[...]
"We can now migrate to lower line widths without any barriers once we add low-k dielectric materials to the process," Joshi said. "After that, optical [techniques] can be pushed to move beyond the 0.10-micron generation."
[...]
_____________________________________________________________________

Goutama
.



To: chic_hearne who wrote (675)7/13/2000 12:28:55 PM
From: vince doranRead Replies (1) | Respond to of 275872
 
Chic - think anyone at the Gateway call will ask about the GHz-Tbird problem?

regards,
Vince