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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Hans de Vries who wrote (2598)	7/28/2000 12:53:06 AM
From: Charles R	Read Replies (2) \| Respond to of 275872

Hans, <I'm starting to take this Single Sledgehammer core = Mustang seriously> AMD guys have been incredibly tightlipped on Mustand/Hammer and this Mustang=1/2 Sledgehammer is a fascinating theory. However, I am told this is not the case. I believe the biggest improvements with Mustang will be SIMD stuff and not 64-bit extensions. Would be pretty cool if the hypothesis is true but I think it is a very long shot. <The Gate, Source and Drain of a transistor are normally placed in a row on the substrate. AMD's design is a 3D design. An etch process stage leaves a rectangular block of silicon. The gate is put on top in the usual way but the Drain and the Source are placed on the vertical sides of the block! The open spaces between the blocks are used for the isolation between the transistors. They are filled with an isolator. The main advantages are: 1) Much higher density: reduced die size. 2) Higher speed transistors: The whole path between Source and Drain becomes shorter. 3) Lower power consumption: The transistor has less contact with the substrate> Interesting. TWY, could you comment on this? Chuck

To: Hans de Vries who wrote (2598)	7/28/2000 1:28:28 AM
From: Pravin Kamdar	Read Replies (1) \| Respond to of 275872

Hans, The S/D contact regions 98 are formed on the vertical side-walls 78 so that only a minimal amount of the horizontal surface 12 of the substrate 10 is used to form electrical contacts. The lateral source/drain transistor 1 realizes a significant reduction in lateral dimension 17 in comparison to lateral dimension 50 of the transistor shown in FIG. 3. The S/D contact regions 98 have a large surface area that results in a reduced contact resistance than is attainable using conventional techniques and structures. A lowering in S/D contact resistance enhances transistor performance. Is dimension 50 the distance between the inner source/drain contact edges on a conventional transistor? If not, is seems like the the source/drain contact regions 6 are not being accounted for in the required lateral dimension (wish I had all the drawings). This sounds like a good idea. With additional benefits of noise isolation and latch-up prevention (the isolation preventing the creation of parasitic lateral bipolars). How many processing steps and mask layers does it add? The thought of AMD using a new transistor design with new processing steps scares the hell out of me. Any manufacturing glitches will kill this stock. Thanks for the info. Pravin.

To: Hans de Vries who wrote (2598)	7/28/2000 9:40:19 AM
From: pgerassi	Respond to of 275872

Dear Hans: Re: New Transistor Design That does look like a good idea for faster smaller transistors. With the adding of two or three additional production masks (This is a quick and dirty calculation (anyone have a better handle?)) this may be quite worth the effort. This looks to be more controllable than Intel's trenched design. We will see if it is incorporated into Mustang. Pete

To: Hans de Vries who wrote (2598)	7/28/2000 10:14:19 AM
From: milo_morai	Read Replies (1) \| Respond to of 275872

<font color=darkblue>Hansdevries excellent info! I like this part of the info. "Applicant(s): Advanced Micro Devices, Inc., Sunnyvale, CA News, Profiles, Stocks and More about this company Issued/Filed Dates: July 11, 2000 / April 7, 1998 Application Number: US1998000056834 IPC Class: H01L 29/00; H01L 29/94; Class: 257/520; 257/336; 257/344; 257/382; 257/384; 257/510; 257/513; Field of Search: 257/508,510,513,514,515,520,521,336,343,382,383,397,413,344,384 Abstract: A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are self-aligned to both the gate electrode and the trench side-walls. A dielectric spacer is formed adjacent the gate electrode and extending to the trench side-walls. In this manner, the spacers essentially cover the LDD regions. Source and drain regions are formed that are adjacent the trench side-walls wherein the spacer serves to protect at least a portion of the LDD regions to maintain a spacing of the S/D regions from the gate electrode edge. In this manner an advantageously lowered EM provided by LDD regions is maintained. In some embodiments of the present invention, S/D regions are formed by implantation through the trench side-walls. Thankyou Sir Milo