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To: Bilow who wrote (48303)7/29/2000 11:03:27 PM
From: NightOwl  Read Replies (1) | Respond to of 93625
 
Thanks Carl,

This is interesting and I think I understand what you are saying. ...Although I reserve the right to make additional erroneous M&P assumptions in the future. :8)

I seem to be unable to retain a valid DRAM schematic in my bird brain for more than 2 ns. But assuming they increase row size, for the moment I believe I grasp the basic rudiments of your power increase analysis.

Am I right in assuming that maintaining the same row size on a 4 bank chip would produce an impossibly large RIMM to produce a 128MB device?

For the life of me I just can't see a good use for this bus design without a major overhaul of the FSB link to the CPU as well as the output to/from the memory to any other subsystem that uses the DRDRAM array.

Ooops, never mind. I think I see why. They don't want to sell a refrigerator with each CPU.

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