To: Bilow who wrote (48395 ) 7/31/2000 10:45:00 AM From: milo_morai Read Replies (2) | Respond to of 93625 <font color=darkgreen>DDR-II, the ESDRAM based Rambus Killer? (HARDWARE) Posted By johan Monday, July 31, 2000 - 9:06:10 AM Our next memory guide will be published wednesday or with a bit of luck even sooner. However, I would like to quote from our yet unpublished part 2: "Ramtron found a more elegant solution. ESDRAM, a sort of cached DRAM, includes SRAM buffers. Those SRAM buffers contain the row data, and the controller can read those buffers instead of the sense amps (see part one to fully understand this). While the SRAM buffers are read, the sense amps can do precharge and refresh operations. In other words, those SRAM buffers can eliminate a latencies like the precharge latency (Precharge time (Trp)). And that is not all. Such SRAM buffers have lower CAS and RAS to CAS latencies, so if the buffers contain the right information, the critical word may be send in 5-6 cycles to the CPU instead of the 7 cycles that we have calculated for "normal" SDRAM. ESDRAM is also based on HSDRAM chips (HSDRAM is also developed by Ramtron) and can be clocked at higher speeds. ESDRAM offers little benefit for streaming applications (only slightly more bandwidth) but in most cases ESDRAM can offer a lot lower "critical word latencies". Why do I quote from an unpublished article? Because according to this document, DDR-II (the next generation of DDR SDRAM) will be based on ESDRAM! This means that DDR-II will offer high bandwidth combined with very low latencies. Combine this with the K8, which could have an integrated north bridge and you get even lower latencies and even higher bandwidth... I think I am going to add a small chapter to the second part. The next generation memory technology battle gets more interesting every day... aceshardware.com Carl I've not had the time to research RMTR but if true and RMBS can't touch them do to patents, this could crush RMBS Milo