SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: semiconeng who wrote (107564)8/14/2000 11:33:00 PM
From: Joe NYC  Read Replies (1) | Respond to of 186894
 
semiconeng,

Sorry Joe, the numbers don't add up....
...A yield of 48%, doesn't sound too good to me.


I said: 3.6 M would be acceptable (but not outstanding) yield.

We may argue about some percentages up and down, for example you said:

Wafer Area / Die Area = Total Die Per Wafer
31,400 / 117 = 268.37 Die Per Wafer

But let's be fair, and count for partial die, and say 250 Die Per wafer.


I am no expert in the field, but I have seen losses on edges and between individual die amount to more than that. Also, I don't know if 117 mm^2 is the official numner. I have used 120 mm^2 for Tbird.

3.6 million chips claimed by Jerry is the number of chips sold (which may be limited by the availability of chipsets). It is also a number that is the worst case scenario for AMD, because they sure don't want to miss it. They will most likely produce more.

I guess these minor points combined will result in a yield in the 50s which again is acceptable (but not outstanding) yield.

Joe



To: semiconeng who wrote (107564)8/14/2000 11:47:05 PM
From: Dan3  Read Replies (1) | Respond to of 186894
 
Re: Sorry Joe, the numbers don't add up

Edge loss alone will account for at least 50 die. Cutting loss takes wafer area used by each die up to about 140mm2. Start at about 175 max for a perfect yield of whole chips from each wafer.

Now remember that it takes about a quarter to go from wafer to chip so Q3 output corresponds to Q2 production when wafer starts at Dresden were ramping up from 600 per week.

So 1500 Austin + 750 (average) Dresden WSPW equals 2250 wafers per week times 175 times 13 weeks gives a max theoretical yield of 5.1 million and a final yield of 70% if they're going to sell 3.6 million chips this quarter.

Intel was getting up to 1 million die per week from a FAB that does 10K wafers per week and is pretty much dedicated to Coppermine. At 104 mm2 the wafer area used would be about 125mm2 to account for cutting losses and an edge loss of about 60 gives a max theoretical yield of about 190 die per wafer. So 10,000 times 13 times 190 is about 25 million out of which they got fewer than 13 million useable die (a 1 million die week was a big deal) and a final yield of less than 52%. And the bin split is lower.

:-)

Dan