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To: jcholewa who wrote (5186)	8/16/2000 11:38:30 AM
From: pgerassi	Read Replies (2) \| Respond to of 275872

Dear JC: Re: P4 The problem with P4@1400 ~= P3@1000 is not a problem iff the sweet spot of P3 is 700 and P4 is 1400 on the same process. Thus, P4@2000 ~= 1.4 * P3@1000, which is great for Intel. However, if the sweet spot of P4 is 1000, then it is very bad for Intel since P4 die ~= 1.5 P3 die. Just where the breakeven spot is depends on a slew of factors. The pushing of P3 onto 0.13u is troubling since it is very obviously a fallback plan, if P4 bites the dust as a pipeline too long (reworded from a "Bridge Too Far"). We shall see. Pete

To: jcholewa who wrote (5186)	8/16/2000 12:23:13 PM
From: Jim McMannis	Respond to of 275872

JC et al... Something you might be interested in... IBM makes advanced Quantum Computer discovery.com Jim

To: jcholewa who wrote (5186)	8/16/2000 12:25:41 PM
From: Jim McMannis	Read Replies (2) \| Respond to of 275872

JC et al... Something you might be interested in... IBM makes first Quantum Computer discovery.com Seems these things do all the calculations in one cycle... Jim

To: jcholewa who wrote (5186)	8/16/2000 1:07:48 PM
From: Petz	Read Replies (3) \| Respond to of 275872

JC, <one pipe for FADD/FMUL/Fetc., and one pipe for FSTORE and similar "maintenance" tasks. Isn't this overall correct? Wouldn't, then, it be more accurate to say that the P4 and P6 have the same number of pipelines (two)?> SSE2 includes multiply/accumulate instructions. Is is possible that P4 can do this in one cycle? I also am skeptical of the P4 1.4GHz = P3 1 GHz school of thought. Worst case, this would only be true if all the code fits in the L1 cache. For more normal code, like business benchmarks the IPC difference does not make that much of a difference, so a 1.4 GHz P4 may be eminently sellable. Petz

To: jcholewa who wrote (5186)	8/16/2000 1:24:10 PM
From: Ali Chen	Read Replies (1) \| Respond to of 275872

Re: IPC gains P2 vs Pentium The fact is that IPC of P2 is SMALLER than Pentium Classic, by as much as 30% if I remember some charts correctly. However, the non-blocking backside L2 cache and pipelined FSB of PentiumPro/P-II/III have tremendous effect on the CPU stall time - reducing it by a factor of 5, as I remember those performance charts (and the L2 speed does not matter much at all). The Pentium Classic (and every other compatible processor) beats P-II in performance on application benchmarks if below 200MHz, but "scales better" if the core frequency is higher. Which is the proof of the said statement about IPC. Regards, - Ali