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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (50106)	8/17/2000 7:22:02 AM
From: Ian Anderson	Read Replies (1) \| Respond to of 93625

You guys are missing the point about both edge clocking in DDR, and prior art to RAMBUS patents. I don't think anybody is disputing that there is prior art for the "method" of both edge clocking of data. Rambus is claiming "aparatus", a design in the silicon of a DRAM, whereby two sets of sense and drive amplifiers from different banks of memory cells are connected to one set of I/O pins, forming a multiplexor arrangement allowing data transfer on both clock edges. That I believe really is novel as far as implementation in DRAM silicon is concerned. The DDR camp might dispute it on the basis that it is really equivalent to using two memory chips with an externally generated inverted clock and connecting their I/O pins together. That argument would probably fall on the basis that the utility (usefulness, ease of use, compactness) of the silicon version is greater, and therefore the implementations are not equivalent. (There is a general principle in Patent Law that you can't glue two or more existing inventions together, and call it your own new invention, unless the combination has a value greater than the sum of the parts. I don't think that Rambus will find this hard to demonstrate though.) Ian

To: Bilow who wrote (50106)	8/17/2000 9:10:21 AM
From: Pluvia	Respond to of 93625

I've not found a link to the technology, but I have no doubt it is out there. The only problem is that it is quite obsolete, so I will have to search through the patent literature. When found, I will post it here. Thanks Carl - great work as always...

To: Bilow who wrote (50106)	8/18/2000 7:44:57 AM
From: John Walliker	Read Replies (1) \| Respond to of 93625

Carl, He said it was a serial interface that ran at 10Mbits/sec, and consisted of four wires: A differential clock, and differential data. The peak transition rate on each wire was 10 million per second, both clock and data, just as in DDR. He said that because of the differential drive and the balanced peak bandwidth between clock and data, it could drive quite long lines. In his lab, he got it to run long enough to hold ten bits in the wire simultaneously. Do you know how he overcame frequency dependent dispersion? Your numbers imply a cable length of about 200m. I worked on a digital television distribution system in 1974 which operated at a clock frequency of around 13MHz (3 x colour subcarrier) without double clocking. The transmission velocity of long strings of the same state was different from that of rapidly alternating bits. This meant that for some data patterns the relative timing between clock and data became too large, even with regenerators at 50m intervals. I would therefore be very surprised if the system you described could have worked reliably without data scrambling before transmission to overcome this problem. It was to overcome such problems that the Manchester coding used in Ethernet was invented. John