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To: Goutam who wrote (5482)	8/17/2000 7:07:22 PM
From: ptanner	Read Replies (2) \| Respond to of 275872

Goutama, Re: "The ceramic packages usually contain the silicon chip in a cavity located in the center of the package." The photos make it look like the chips are slightly above the surface of the package -- likely why they provide the four pads to help support the heat sink evenly. amd.com amd.com www6.tomshardware.com www6.tomshardware.com www6.tomshardware.com I wasn't going to provide a link but then I couldn't decide which I liked the most. Of course, some here probably have the actual processors or other direct knowledge anyway. -PT

To: Goutam who wrote (5482)	8/17/2000 7:40:42 PM
From: Joe NYC	Respond to of 275872

Goutama, I also read a couple of messages on the other boards about people cracking the core while trying to attach the heatsink. I believe they assumed they cracked the core when all it was just chipping of the ceramic package at the corners. You are right. Most of the people who mentioned chipping not cracking. And most reported that the CPU still worked. I hope I will have better luck. I am expecting 2 Tbirds, both 1 GHz early next week. They are delayed. I got a story from the vendor that their shipment that was coming directly from AMD was held up at the customs. Just by looking at the pricewatch, AMD must be shipping a lot of Socket A parts. Thunderbird CPUs are now 19 pages, up from 15 pages on weekend, Duron is 14 pages. Joe

To: Goutam who wrote (5482)	8/17/2000 7:45:01 PM
From: semiconeng	Read Replies (3) \| Respond to of 275872

How can they crack the core? The ceramic packages usually contain the silicon chip in a cavity located in the center of the package. Actually, that's not quite how the Controlled Collapse Chip Connect (C4 Bump Process) works. It's true, that semiconductor manufacturers USED to place the chip front side up in the package cavity, attach gold wires to connect the bond pads to the package pins, cap the cavity with a ceramic cover, and attache the heat sink to the cover. Not anymore. Now, at the end of the Fab line, an extra layer of "Adhesion Metal" is sputtered onto the wafer. Lithography applies resist, with openings over the Bond Pads, the wafers are then placed into an "electroplating" type machine, which applies tin/lead solder into the openings, creating an ahesion metal/solder stacked column above each bond pad. The resist, and excess adhesion metal is etched away, and your left with a stack attached to each bond pad. The wafers are then placed in a bath, and just enough temperature is applied to collapse the column into an adhered solder ball on top of each pad. The wafers are then sorted and tested, cut up, and the good die are "Flipped Over" (ie: Flip Chip), aligned to connector pins on the package/board. Heat is applied to slightly melt the solder bumps, soldering the bond pads directly to the package pins. There is a bit of space left between the "Face Down die, and the circuit card, which is filled in with some sort of epoxy resin sealer, and that's what "Looks Like" ceramic packaging. A good explanation can be found here: layers.com Why do it this way? Several Reasons: * As microprocessors became more complex, more connections and therefore more bond pads were needed. In "Wire Bond", the pads MUST be located around the edge of the die. Sometimes you needed to make the die larger JUST to accomodate the required number of bond pads. With the bump process, they can be located ANYWHERE on the die, reducing die size. * Cost. Gold Bond Wires cost money, and are more difficult to work with. Solder on the other hand is cheap, and everybody can work with solder. Also, this technique allowed the elimination of the ceramic and/or plastic package. * Reliability. Ceramic packaging was a "sandwich" kind of deal, and depended on the reliability of the sandwich sealer to keep dirt/moisture out. Since Flip Chip injects the epoxy resin in all the cracks and crevices between the die face, and the circuit card, it effectively "seals" the die completly. * Thermal. With past packaging, the die was sealed up in the package, and the heat sink applied to the package. With flip chip, the BACK of the die is EXPOSED, allowing connection of the heat sink DIRECTLY to the die. The only disadvantage, is that the die IS exposed, so any kind of mis-handling while installing and/or removing the heatsink, can crack the epoxy sealer and/or die itself. BE VEWY VEWY CAREFWEL WIT DEEZ TINGS..... :-) SemiconEng