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To: Don Green who wrote (50338)8/19/2000 12:55:05 AM
From: Don Green  Read Replies (1) | Respond to of 93625
 
Plan a 'platform-ready' path
08/18 23:47 EST
Aug. 18, 2000 (Electronic Buyers News - CMP via COMTEX) -- A few years ago, the
DRAM market only comprised a couple of device modes, fast page and extended data
out (EDO), with two or so device organizations, typically x1 or x4. The market
has since diversified due to expanded applications that require various types of
DRAMs-high bandwidth, high density, low density, wide architectures, narrow
architectures, low power, standard-power ECC, or non-ECC.

Synchronous DRAM (SDRAM) accounts for about 90% of current DRAM usage. By the
end of 2000, Rambus and double-data-rate (DDR) combined may grow to be about
10%, while EDO/fast page will comprise about 5%.

To deal with this growing diversification and the resulting supply issues, OEMs
should align with DRAM vendors who are platform ready-meaning the vendor is
prepared to produce any DRAM modes that customers require (EDO, SDRAM, DDR, or
RDRAM) in large volume with high product availability. The vendor will also have
ample front-end and back-end fab availability with the required test equipment
and packaging at the back-end and can ramp up production as market demands grow.

This fragmentation emanates from OEMs learning that different DRAMs operate
better in different applications based on different system requirements.

Some networking equipment has long product life cycles because it is designed to
be field upgradable and must stay compatible with other existing systems. In
this case, the same type DRAM is used for a long time. Some large network OEMs
have introduced EDO DRAM-based systems with product life cycles of 10 years.

The PC segment of the market is diversifying within itself. High-end PCs are
using Rambus, and as prices come down, Rambus could penetrate mid- to low-end
PCs. Due to the high Rambus premium, these lower-end PCs must, for now, use more
modestly priced DRAMs. The current platform is 100-MHz SDRAM, moving toward 133
MHz. Some PC OEMs are considering DDR SDRAM systems based on AMD's Athlon
processor, which supports PC266. Athlon's front-side bus is a 133-MHz DDR bus,
matching the PC266. As a result, DDR will gain acceptance in volume PCs that use
the Athlon chip.

Servers are a fast-growing market, continually spurred by the Internet and Web
hosting, so data integrity is critical. If a single device fails, the so-called
chip kill must be detected and data flow adjusted accordingly. Therefore, those
applications require x4 devices. Also, average memory requirement is now over 1
Gbyte per system with some servers required to support up to 64 Gbytes. As a
result, power consumption is critical. Currently, the device of choice is the
SDRAM, and is moving toward DDR.

The graphics segment of the market is mostly using high-speed SDRAMs up to 200
MHz in a wide-bus environment (64-, 128-, and at the high end, 256-bit- wide).
Graphics can use higher-frequency SDRAMs due to the nature of the application
(point to point), currently using 4M x 16 DDR devices running at 166 MHz. But
these high-end applications will require 200 MHz by the end of this year and 300
MHz toward the second half of 2001.

Product demand comes from OEM system segments that require specific memories.
Since each OEM has its own product marketing strategy and pricing requirements,
most can't plan beyond six months. OEM DRAM purchasing decisions are made on a
best price, best performance basis about six months before products using those
DRAMs are launched.

A leading DRAM supplier has to be ready to meet customer demand, regardless of
the required DRAM technology. This diversification of DRAM modes calls for major
design and development resources to rapidly bring new product to market to
comply with next-generation system needs. Unfortunately, smaller DRAM vendors
may not have the critical engineering, fabrication, or capacity resources to be
platform ready.

If a small DRAM vendor has only a single fab and wants to produce SDRAM, DDR,
and Rambus, the end product will prove to be less cost-effective because the
vendor isn't getting maximum economies of scale. Large vendors endowed with
multiple fabs have the luxury of allocating fab-specific products-DDR in one
fab, Rambus in another, and SDRAM in yet another. The benefit to OEMs is when
volume increases, the vendor can add capacity.

Small DRAM vendors are severely challenged to maintain a state of platform
readiness given this new DRAM environment. From the OEM perspective, customers
want a one-stop shop. They don't want to buy their DDR from one vendor, Rambus
from another, and SDRAMs from yet another.

-Farhad Tabrizi is vice president of strategic marketing and product planning at
the DRAM Business Unit of Hyundai Electronics Industries Co. Ltd., San Jose.


ebnonline.com


-0-



By: Farhad Tabrizi
Copyright 2000 CMP Media Inc.



To: Don Green who wrote (50338)8/19/2000 6:54:15 PM
From: Rich1  Respond to of 93625
 
Since I think the news from IDf will impact Rambus I bought a 20 contract straddle friday. We shall see.



To: Don Green who wrote (50338)8/20/2000 7:36:56 PM
From: Mihaela  Respond to of 93625
 
Intel gems on display at forum
By Ken Popovich, eWEEK
August 18, 2000 12:34 PM ET

Intel Corp. will march into its Developers Forum next week with two significant new processor announcements, including the company's first 1GHz Pentium III Xeon and a new StrongARM chip for mobile devices, according to sources.

Another highlight of the three-day conference in San Jose, Calif., will be the demonstration of third-party workstations and servers featuring Intel's forthcoming 64-bit Itanium processor. The chip, which has been under development for seven years and is designed to help Intel finally break into the high-end server market, is scheduled to debut next quarter after numerous delays.

In delivering the opening keynote address on Tuesday, Intel CEO Craig Barrett will announce the company's 1GHz two-way Xeon processor for workstations and servers, as well as its second-generation StrongARM processor, the SA-2, for mobile devices. Intel's 1GHz Xeon, with 256KB of cache, was originally scheduled for release later this year.

The company's fastest two-way Xeon to date clocks at 933MHz, and its fastest four- and eight-way Xeons, featuring 1MB and 2MB cache sizes, respectively, operate at 700MHz. Last month, Intel scrapped plans for a "large cache" 800MHz Xeon after computer manufacturers balked at integrating the processors with their systems so soon after the May ship date of the 700MHz Xeon.

The SA-2 is the first StrongARM designed by Intel since its acquisition of Digital Equipment Corp.'s semiconductor operations in 1998. The embedded processor is designed to power palm-size devices, smart phones and other mobile systems.

During the conference, Intel also will highlight a peer-to-peer business initiative, display a concept PC based on the company's upcoming Pentium 4 and offer a glimpse of Universal Serial Bus 2.0 products slated to hit the street by year's end.

What about Rambus?

One issue expected to attract as much attention at next week's gathering as it did at the last developers conference six months ago will be Intel's stance on Rambus memory technology. Once again, industry observers will try to gauge whether Intel has weakened its commitment to the memory interface.

In February, Intel called for its future processors to be packaged with Rambus DRAM (dynamic RAM) instead of the more popular and less costly SDRAM (synchronous DRAM).

But since then, several major developments have fueled speculation that the company's stance is wavering -- including its recall earlier this year of its 820 chip sets equipped with SDRAM, due to a faulty memory translator hub.

Major OEMs at the last developers conference only showed Intel-designed Itanium systems disguised as their own.

In effect, Intel systems known as "software development vehicles" were merely placed in boxes bearing the vendors' brand names, such as Compaq Corp., Dell Computer Corp. and Hewlett-Packard Co. But the exhibit touting the prototype 64-bit machines made no mention of that fact.

www8.zdnet.com



To: Don Green who wrote (50338)8/20/2000 7:51:50 PM
From: Mihaela  Read Replies (4) | Respond to of 93625
 
Intel to spill Pentium 4 details at forum
By: Michael Kanellos, CNET News.com
8/20/00 3:36:00 PM
Source: News.com

Intel will fill in the details on the Pentium 4 at its developer forum in San Jose, Calif., this week and will show off new chips for cell phones and handheld computers.
The Pentium 4 will feature a completely new architecture called "NetBurst" designed to handle tasks--such as data encryption, video compression or Napster-like peer-to-peer networking--that have grown in popularity with the Internet, said Albert Yu, senior vice president of the Intel Architecture Group.

"It will be the highest-performing processor for PCs," Yu said. "We're moving into streaming video; speech has become much more commonplace than a year ago. Peer-to-peer has been around for a long time, but it is now being recognized as the computing paradigm of the future."

New subsystems inside the NetBurst architecture will enable the processor to churn more data at a faster rate, Yu said. A micro-engine called the "Rapid Execution Engine," for example, will run at twice the speed of the processor and will handle frequently repeated tasks, such as addition and subtraction calculations.

In a preview of the chip at the company's headquarters, technicians showed how a Pentium 4 computer can rapidly render, or draw, 3D images downloaded from the Internet. That sort of processing power could make it easy for sellers on eBay to post virtual representations of their products, for example.

The chip, which will debut at 1.4 GHz and arrive in the fourth quarter, represents the first complete architectural overhaul of the company's processor line since 1995, when the original Pentium emerged. It will contain 42 million transistors, compared with 28 million for the Pentium III.

For Intel, the chip's arrival couldn't come sooner. Manufacturing missteps and increased competition from Advanced Micro Devices have eroded the chip giant's once-unassailable dominance in the market for processors for performance PCs.

Yu and CEO Craig Barrett will be the first keynote speakers at the Intel Developer Forum, a three-day event that begins Tuesday in San Jose. The event largely serves as a forum for Intel and its associated developers to unfurl their road map for future technology.

Along with the Pentium 4, the company will provide updates on Itanium, the long-awaited 64-bit chip for servers.

While the Pentium 4 and Itanium will be targeted toward the performance end of the spectrum, the company will also emphasize the device market.

On Wednesday, Ron Smith, general manager of Intel's wireless computing group, will announce a new line of StrongArm chips--small, energy-efficient chips for handhelds and cell phones. Formerly code-named StrongArm 2, the new chips will come out at the end of the year.

"We are going to be introducing a variant of the StrongArm under a new brand name," the spokesman said.

One of the first customers for the chip may be Palm. The handheld computer leader has already said it plans to adopt processors based on the ARM architecture, a processor design licensed by England's ARM. StrongArm chips remain one of the most popular versions of the ARM design. Palm prototypes containing 200-MHz StrongArm chips were shown off at technology events earlier this year.

Still, the details surrounding the Pentium 4 will likely be the highlight of the conference. Since last October, chip shortages, combined with AMD's success with Athlon, have put the company on the defensive in the high end of the market.

Though analysts have expressed varying opinions on how well the Pentium 4 will perform, Yu said the NetBurst architecture will bring several new capabilities to the market.

The Rapid Execution Engine, for example, will "turbocharge a piece of the engine," Yu said, by shifting repetitive tasks out of the main processing and into a specialized, accelerated computing center inside the chip. The Rapid Execution Engine will then be complemented by an Execution Trace cache, a fast reservoir of memory designed to keep the engine packed with data.

Other features will exist to speed data flow and make it more efficient. "Advanced Dynamic Execution" will speed processing by allowing the processor to recognize parallel patterns and prioritize tasks. In all, the chip will be capable of handling six instructions per clock cycle over extended periods. The Pentium III typically handles three.

The chip also comes with 144 new multimedia instructions for better graphics and sound. By rewriting their software with the instructions in mind, software developers will be able to improve application performance.

"The Internet is going from a text kind of thing to something more visual," Yu said.

In addition, the Pentium 4 will contain a 20-stage pipeline. The pipeline is a processor's assembly line. While this means the Pentium 4 will have a line twice the length of the 10-stage Pentium III, the longer pipeline will create room for speeding up the chip.

Whether Intel can manufacture the chip in volume will also be a major question at the conference and beyond, as the company has struggled to produce 1-GHz Pentium IIIs in significant volume.

Yu said the Pentium 4 will be in volume production toward the end of the year. An Intel spokesman said that "hundreds of thousands" of the chips will come out this year.

Historically, that would mean the Pentium 4 will be in shorter supply than when the Pentium II or other new chips came out, but likely in larger quantities than the first 1-GHz Pentium IIIs.

In addition, as with the original Pentium, the basic architecture of the Pentium 4 will become the foundation of the company's processors for the next five to seven years. Following Moore's Law, this would lead to chips running at more than 11 GHz in 2006.

"A microarchitecture typically lasts five to seven years, and this one is no exception," Yu said.

cnetinvestor.com