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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (6167)8/22/2000 9:36:13 PM
From: MaverickRespond to of 275872
 
Deep pipe means huge penalty for branch target cache miss as it has to be flushed. Also affected is long latency. INTC cheated the MHz race by deepening the pipe. Apps need to be recompiled to take advantage of the pipe. Therefore, small on-die L2 worsens the performance.



To: Scumbria who wrote (6167)8/24/2000 7:32:12 PM
From: TimFRead Replies (2) | Respond to of 275872
 
A deep pipeline requires a lot of die area for latches. Also, the high clock rate requires large drivers.

Of course, the itsy-bitsy L1 data cache saved some die area.....

I've never designed any microprocessors but you would think that if it has a 217mm2 die it the % increase from making the L1 a bit bigger would be worth it considering the
improved performance.

Tim


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