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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Proud_Infidel who wrote (108225)	8/24/2000 11:14:14 AM
From: Joey Smith	Read Replies (1) \| Respond to of 186894

re:Countering claims made recently by an industry microprocessor research firm, Intel Corp. at this week's Intel Developer Forum here said the upcoming Pentium 4 has no deep pipeline performance penalty....... The Pentium 4 also features a Level 1 on-chip cache that executes already decoded instructions, thus eliminating latency delays. Could Scumbria be dead wrong on this issue? Hmmm. Joey

To: Proud_Infidel who wrote (108225)	8/24/2000 11:21:31 AM
From: Paul Engel	Read Replies (2) \| Respond to of 186894

Brian - Re: "Bert McComas, an analyst at InQuest Research Inc. in Gilbert, Ariz., " McComas put together AMD's Platform 2000 FLoparoo a few weeks ago - probably under contract from AMD. Since there was essentially NO AMD PLATFORM news, McCOmas concentrated on spewing anti-Intel news, bashing the Pentium IV specifically. Ever since then, the stupid news media - Jack Robertson in particular - has been regurgitating McComas's anti-Intel crapola as if he was the second coming of Christ. And, nobody ever bothered to report McCOmas's credentials to validate (?? HAH !) who he was to criticize any CPU let alone Intel's. At this point, MCComas appears to be a paid AMD flunkie. Paul

To: Proud_Infidel who wrote (108225)	8/24/2000 3:10:46 PM
From: EricRR	Read Replies (1) \| Respond to of 186894

Tench- What do you think: Jeff Austin, Intel's IA-32 architect launch manager, said the Pentium 4's 20-stage pipeline suffers no penalty for pre-fetch misprediction because of its use of the NetBurst technology A is "prefetch" misprediction the same as a general "branch" misprediction penalty? As I understand it, prefetch is where a specific piece of code or data is requested into the cache before it is needed, in anticipation of its imminent requirement. Is the above quote just "spin" on the idea that the branch mispredict for code in the trace cache will only be 20 clocks, vs 26 for code outside the trace? (BTW are those numbers right?) Did you say yesterday that P3 has a 13 clock mispredict penalty? Or was that total pipe size? Sounds to me like Intel is setting themselves up for more polymorphic code problems, which by their nature have high mispredict rates. Are Willimettes decoders really insuffient to supply the pipe without trace cache micro-op reuse? This the opposite of what you want for servercode. Intel makes great compilers (i'm using one right now!) but they missed the boat on the future of software design.