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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Jdaasoc who wrote (51083)	8/24/2000 9:13:51 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 93625

John, the whole platform world is going toward fewer signal pins and high transmission speeds, despite what the anti-Rambus FUDsters claim. Even AMD's LDT technology transmits data at 1.6 Gbits per second per pin, but the width of each LDT port will be 8, 16, or 32 bits per direction. That trend would suggest that perhaps RDRAM-800 came a little too early for its time, given that "normal" signaling speeds didn't exceed 266 Mbits per second per pin. But the trend itself is real. Tenchusatsu

To: Jdaasoc who wrote (51083)	8/24/2000 9:53:02 PM
From: Bilow	Respond to of 93625

Hi Jdassoc; OTOT Re Intel's graphics serial bus... I don't know anything about the serial graphics bus being developed by Intel, is there some source of public information I should be aware of? Of course this has little to do with RDRAM or RMBS, but it is of slight interest, I suppose. In general, there is nothing wrong with serial interfaces. Engineering is almost always about specific details, not about generalities like "serial is no good". You are no doubt well aware of this. The devil is in the details. That said, I guess I can comment on what I, personally, would like to see in a high speed serial interface for graphics, and how that would differ with the POS that Rambus came up with. Of course there are many ways of specifying a reasonable interface, this is just the ideas that immediately come to me. Just because the Intel spec will differ from mine considerably does not mean that I wouldn't think that the Intel spec is a great idea. But to the extent that they do use the same ideas I have, well they obviously copied me, and owe me royalties big time. (G) (1) Make it point to point, preferably with fixed source and destination. The basic reason is to maximize the amount of bandwidth you get per cm width of PCB. That is, you want a high speed interface to not occupy a lot of PCB space. The AMD LDT uses this technique, and it is not at all new. Seymour Cray used the same thing all over the place 30 years ago. The technical reasons why this is preferable are too complicated to go into, but basically revolve around the simplicity of the design. (2) Make it pass signals DDR style, with a differential clock, which is source synchronous. But leave the signals single ended. This is similar to how RDRAM works. DDR is clocked source synchronous but some of the clocks are single ended instead of source synchronous. I read somewhere that DDR-II is going to fully differential clocks. The reason for this is that the jitter on any one clock line cuts the margin on 16 (or whatever your width is) data pins, while the jitter on any one data pin only cuts margin on that data pin. Consequently, the low hanging fruit is in keeping the clocks clean. (3) Use SSTL or another symmetric, low swing, modern signal level. You want to choose a logic definition that doesn't require all the ASIC guys to build interfaces that are useful only for your serial interface. RDRAM mostly uses RSL (Rambus Signal Level), which is a rare, unusual and patented signal definition, but it also uses a version of CMOS. It is better to have just one signal level definition, like DDR has, as it improves consistency for the engineers. (4) Pass the address information on the same lines as the data. I know that this is kind of radical, but it allows a better bandwidth mix between address and data. The current AGP uses this technique, after a fashion, but Rambus does not. Of course DDR also does not share address and data. The place where this really helps your average bandwidth per pin is when you pass a lot of data. On the other hand, when you are reading little bursts, you still get about the same pin utilization as when you have specific pins for each function. -- Carl