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To: EricRR who wrote (6829)	8/28/2000 8:34:51 PM
From: Scumbria	Read Replies (3) \| Respond to of 275872

Ratbert, Re: DeMonde An 8KB dcache is just one aspect of the design and you cannot read too much into it in isolation. The performance of the memory system depends on both levels of caches, the system interface and chipset, and how the execution core interacts with the memory system. This is partly true, but L1 misses insert quite a few bubbles, even if they hit in the L2. A small L1 cache is pretty bad for performance in high MHz processors. The second generation Alpha core EV5 had 8 KB L1 caches and it was a performance leader for years against chips with a lot bigger L1's. Lousy argument. The big L1 chips ran at 1/4-1/2 the clock speed of Alpha. Not the case with Willy vs. Athlon. (0.13 Athlon may be faster in MHz than 0.18 Willy) Remember, x86 is very register poor so the L1 dcache essentially acts as an extended register file. True, but works against the rest of his argument below... Performance of GHz class MPUs is determined by the fraction of accesses that go off chip far more than the L1 miss rate or L1-L2 traffic levels (unless there is an on-chip bottleneck from a bad design mistake). L2 access speeds are much too slow to be suitable for storing register operands. RISC machines can access the register file in one clock. All things considered, the small dcache on Willy is going to hurt performance significantly. Is this guy an Intellabee? Scumbria