To: Bilow who wrote (51649 ) 8/29/2000 6:58:21 AM From: NightOwl Read Replies (2) | Respond to of 93625 Hi Carl, In my never ending quest for Mom & Pop immortality, once again I have been plumbing the depths of EE Design as applied to memory chip development. <g> But I have arrived at a rather substantial brick wall - through which I am unable to drive so much as a beak. Completely ignoring RMTR for the present, as well as the hatred of the major Fabs for anything having to do with RMBS, can you suggest a reason for the absence of any effort by RMBS to have DRDRAM's core redesigned so as to take advantage of the performance enhancements of say: FCRAM, 1T-SRAM, CDRAM, or VC-*DRAM? There seem to be lots of IP options out there which could be put to good use resolving the latency problems of DRDRAM. In particular I would think that some form of the FCRAM design that could be of some use to DRDRAM, particularly if they are "mulling" a reduction in the number of internal banks. Granted there would be a trade off in that such a DRFcDRAM chip would lose a portion of the reduction in die size achieved by moving to a 4-bank structure. But that would seem to be a very small price to pay if such a redesign could give them a true performance advantage over SDRAM/DDR. I am assuming that such a "collaboration" is being hindered by a failure of RMBS and the companies with such cache technology to arrive at an agreeable cross-licensing arrangement. Or is there a greater technical difficulty involved in such a design effort? Thanks for any opinions you may have on this. My reason for asking goes to the question of the value of DRDRAM IP. If its latency profile could be improved substantially, it might be considered valuable at some future date or if owned by, say a Fujitsu, or some other company with complimentary IP. 0|0