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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: vvga who wrote (123352)	8/31/2000 9:34:34 AM
From: porn_start878	Respond to of 1570543

1000MB/s is referring to what exactly? To the scores posted at 2cpu : 2cpu.com

To: vvga who wrote (123352)	8/31/2000 9:57:31 AM
From: Daniel Schuh	Read Replies (1) \| Respond to of 1570543

Sure, vvga. I'm used to Rambusian arithmetic, along will all the other dubious logic and bogus pronouncements of the dedicated Rambus flackmeisters, but just for entertainment: How, exactly, did you calculate 6000 MB/sec for dual PC800 Rambus channels? Even theoretically? As for pins, they're cheap, and DRDRAM is expensive. Intel really blew that calculation, chip area turned out to be a much bigger factor, in memory cost anyway. You might want to check the pin count of the P3 vs. P4 sometime, I imagine Intel is a lot more worried about the P4 die being more than twice as big than they are about the extra pins in terms of production cost. Cheers, Dan.

To: vvga who wrote (123352)	8/31/2000 10:54:48 AM
From: jcholewa	Read Replies (2) \| Respond to of 1570543

> Pins baby... I'm going to go out on the edge here and assert that pins are somewhat irrelevant. The sole advantage of having fewer pins is to reduce prices. Number of pins were (years ago) expected to be a problem, cost-wise, for chipset/memory implementations. For some reason, this has not happened (per-pin costs have dropped such that number of pins aren't as much of a worry). Meanwhile, in order to implement other advantages of DRDRAM, there are cost increases orders greater than the savings generated by the fewer pins. So, pincount isn't really a good ground to stand on to defend DRDRAM. There are other, much better reasons to fight for DRDRAM. Pins aren't it. > > I believe that the K7 with DDR266 will nearly triple it's KT133 scores, or reach close to 1000MB/s, still 30-40% > > under P4, but it will show that it's a chipset concern not a memory type thing... > 1000MB/s is referring to what exactly? I believe he is talking about real world tests, not bandwidth derived through calculation. > DDR chipset bandwidth to memory is more like 266 MHz * 16 B/cycle = 4000+ MB/sec peak. You'd get anywhere from > 30 to 70% utilization for ~2000 MB/s measured. > P4 will have dual RAMBUS 800 channels for around 6000 MB/sec peak and around the same utilization -- except when > we invent some "better" benchmarks... :) Hmm. Are you sure your calculation are accurate? Here is what I math out: PC2100 (sdram): 2 (ddr) x 133.33 (mhz) x 8 (byte width) = 2133.33MB/s. PC800 (drdram): 2 (ddr) x 400 (mhz) x 2 (byte width) = 1600MB/s. PC800 (dual channel drdram): 1600 (drdram bandwidth) x 2 (channels) = 3200MB/s. I won't comment about efficiency, since I'm not quite certain about its veracity. According to most third party testing DRDRAM at 1.066GB/s peak does not significantly outperform SDRAM at 0.800GB/s peak across the board -- the nature of the applications seems to depend on different facets of memory. Nonetheless, I will keep an open mind on the matter. Bandwidth efficiency is an unknown to me, and I will keep observation over as wide a range of benchmarks as possible. But I suggest you do, as well. I will also make a note about the new revision of Rambus memory that Intel is pushing, called something along the lines of '4i'. It reportedly will drop the number of banks per module from 32 to 4 (in order to increase binsplits and yields). I seem to recall that number of banks was the main quoted factor when some people talked about DRDRAM's bandwidth efficiency superiority. I am curious how this variable will be affected by the change in the memory spec.