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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: jcholewa who wrote (123361)	8/31/2000 7:52:58 PM
From: vvga	Read Replies (2) \| Respond to of 1570549

>Im going to go out on the edge here and assert that pins >are somewhat irrelevant. The sole advantage of having fewer >pins is to reduce prices. Number of pins were (years > ago) expected to be a problem, cost-wise, for >chipset/memory implementations. For some reason, this has >not happened (per-pin costs have dropped such that number >of > pins aren't as much of a worry). Meanwhile, in >order to implement other advantages of DRDRAM, there are >cost increases orders greater than the savings generated by >the > fewer pins. > > So, pincount isn't really a good ground to stand >on to defend DRDRAM. There are other, much better reasons >to fight for DRDRAM. Pins aren't it. Two DDR SDRAM "channels" will cost a boat-load of pins, not just a measly 30 pins, more like 100 pins. Yes you can build a dual DDR controller, but it may bump you into a significantly more expensive package.

To: jcholewa who wrote (123361)	8/31/2000 8:05:43 PM
From: vvga	Respond to of 1570549

>Hmm. Are you sure your calculation are accurate? Here is >what I math out: > > PC2100 (sdram): 2 (ddr) x 133.33 (mhz) x 8 (byte >width) = 2133.33MB/s. 2 (ddr) * 133 (mhz) * 16 bytes wide = 4000+ 16 * 8 = 128 bits (AGP 4x on 32 bit bus). The nice thing with integrated graphics is that you can connect directly to the memory switch (no more internal AGP), so you effectively run at 4000+ MB peak. The CPU can burst from memory at this rate as well. > PC800 (drdram): 2 (ddr) x 400 (mhz) x 2 (byte width) >= 1600MB/s. > PC800 (dual channel drdram): 1600 (drdram bandwidth) >x 2 (channels) = 3200MB/s. > > I won't comment about efficiency, since I'm not quite >certain about its veracity. According to most third party >testing DRDRAM at 1.066GB/s peak does not significantly > outperform SDRAM at 0.800GB/s peak across the board >-- the nature of the applications seems to depend on >different facets of memory. > > Nonetheless, I will keep an open mind on the matter. >Bandwidth efficiency is an unknown to me, and I will keep >observation over as wide a range of benchmarks as > possible. But I suggest you do, as well. My guess is that Intel will attempt to rewrite or influence benchmarks to reflect RAMBUS's advantages. There is some validity to RAMBUS's claims of a more efficient architecture -- remember most benchmarks and performance applications were tuned on SDRAM system. > > I will also make a note about the new revision of >Rambus memory that Intel is pushing, called something along >the lines of '4i'. It reportedly will drop the number of >banks > per module from 32 to 4 (in order to increase >binsplits and yields). I seem to recall that number of >banks was the main quoted factor when some people talked >about > DRDRAM's bandwidth efficiency superiority. I am >curious how this variable will be affected by the change in >>the memory spec. The funny thing about this development is that it completely goes against RAMBUS's claims of a "better" memory architecture. The reasoning went : if we can keep more open pages, the AVERAGE latency from memory will go down since there is a higher probability of hitting an open page. Now they are backsliding on this for the sake of saving logic area on the DRAM die. Logic is particularly expensive to implement on traditional DRAM processes.