Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: f.simons who wrote (7214)	8/31/2000 8:42:59 PM
From: Petz	Read Replies (3) \| Respond to of 275872

frank, I've heard that when Intel designs a chip they do all the layout gate by gate. But AMD uses a cell based design which may take more transistors to accomplish a function which isn't in the library, but is of course much faster to design and test. Perhaps when CPU's got past the Pentium III level of complexity, the "time to market" of the Intel approach became too much of a liability, leading to shortcuts in design or fewer iterations in design. OTOH, the AMD approach to using standard cells had a much shorter design time than Pentium IV so it doesn't (yet) have to compete with a 7th generation Intel design. The penalty of the AMD approach, a larger number of transistors seems to be mitigated by a more aggressive manufacturing technique which squeezes them into less space. Here's the die size and transistor count for the P4, Athlon and P3: Pentium 4 = 42 million transistors, dies size 217mm Thunderbird = 37 million transistors, die size 110mm (120?) Pentium 3 = 28 million transistors, die size 100mm It's tough to figure out what's going on here -- it appears that the P4 is nearly 50% larger than it should be based on Intel's typical transistor density, while the higher transistor density of Athlon vs. P3 is nothing to sneeze at. Back in the K6 days AMD achieved greater transistor density by having an extra metallization layer on the chip compared to Intel. I'm not sure whether this is still true for Athlon vs. Coppermine. The agressive AMD layout with higher density as well as the use of copper were clear risks but it appears that, learning from experience with aggressive design, AMD is now able to cash in on it. I believe the cell-based design approach may also explain the extraordinarily low number of errata in the Athlon design, and, conversely, explain how the Pentium 1.13 recall happened. Simply put, the more interconnected circuit elements there are, the more testing has to be performed. Petz