Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: that_crazy_doug who wrote (123466)	9/1/2000 5:19:44 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 1580019

Doug, <That's one reason why I'm glad AMD opted to have SSE (and SSE2?) support with sledgehammer even though they're dropping TFP which probably would have been a bigger performance booster.> Yeah, I noticed in the x86-64 guide that AMD published, there seems to be support for SSE. I wasn't sure, though, particularly since AMD isn't exactly going to the rooftops announcing SSE support. But I'd say SSE support is a definite plus for Sledgehammer. TFP? What's that? The RISC-like FPU that AMD announced last year? What happened to that? I guess having 16 128-bit SSE registers should be more than enough for floating-point, especially since they're going to be FP extensions anyway. Tenchusatsu