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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (123469)9/1/2000 5:57:10 PM
From: that_crazy_doug  Respond to of 1580032
 
<< TFP? What's that? The RISC-like FPU that AMD announced last year? What happened to that? I guess having 16 128-bit SSE registers should be more than enough for floating-point, especially since they're going to be FP extensions anyway. >>

TFP was technical floating point and you're correct it was the risc like fpu they announced last year. It seems to have been canned for SSE. I don't think the performance trade off was good, but it's an excellent deal in compatibility as they won't have to fight for software support.



To: Tenchusatsu who wrote (123469)9/2/2000 12:36:35 PM
From: Scumbria  Read Replies (1) | Respond to of 1580032
 
Ten,

It will be interesting to see how AMD will handle SSE L2 cache preload operations. Intel uses an inclusive L2, whereas AMD uses an exclusive L2, and this will raise some interesting policy decisions for AMD architects.

Scumbria


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