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To: Tony Viola who wrote (7390)9/2/2000 2:56:10 PM
From: muzosiRead Replies (1) | Respond to of 275872
 
re: ...most instructions are very simple, like add and subtract, and can be done in one or two levels of logic.

I'd love to see a 32 bit adder in two levels of logic. It would help me a lot. The best I can think of is a variable length carry skip adder which would be at least 4 levels of logic.

You can certainly do an AND in 1 level of logic though.

Muzo



To: Tony Viola who wrote (7390)9/2/2000 5:14:51 PM
From: ScumbriaRespond to of 275872
 
Tony,

WRT the 2 cycle cache access, do you know that it's a bottleneck, especially with a small cache?

Regardless of the cache size, you still need to do address calculation, translation, tag lookup, compare, mux setup, and data read. It is a serious mistake to do this in 2-cycles in a deeply pipelined design.

Scumbria


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