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To: muzosi who wrote (7393)	9/2/2000 3:55:11 PM
From: Bilow	Read Replies (4) \| Respond to of 275872

Hi muzosi; Re: "I'd love to see a 32 bit adder in two levels of logic." I could easily design a 32-bit adder that had only two stages of even simple NAND gates. Just make a Karnaugh map for the function, and decode it into sum of products. A computer would be useful for doing this. Of course I would have to use NAND gates with a couple thousand inputs... -- Carl (Maybe he was talking about two stages of logic, rather than levels. There are probably plenty of VHDL designers out there that if it weren't for "*.unsigned.all" would end up with adders built just the way indicated. LOL!!!)