To: Krowbar who wrote (5190 ) 9/5/2000 2:06:15 AM From: wily Read Replies (1) | Respond to of 8393 Del, here's my picture of dividing the smooth part of the I-R curve into 4 levels for 2 bits of storage: frontiernet.net What works best for me is to compensate for temperature at the time of writing to the cell. You want to program the cell to a specific resistance for each of the 4 levels, independent of what temperature the chip is at. Since resulting resistance is highly dependent on chip temperature, you have to find a way of reliably compensating for temperature fluctuations. The method I propose is to have a cell or a group of cells that are dedicated test or reference cells (actually you would want a cell or a group of cells for each programming level) Every second or so (chip temperature is not going to change THAT fast) you send a programming pulse to the test cell and see what the resulting resistance is. The first pulse you send will have a current right in the middle of the test range. Referring to the picture, for the #3level, your first pulse would be at 78.4uA. If the resulting resistance was, say, 250,000 Ohms, you would try a higher current, and the one you would pick would be at the high end of the range for level 3, or I2 = 80.6uA. Suppose this produces a resistance of 150,000 Ohms. This is too low, so you go halfway back in the other direction, and so forth, doing a binary-feedback search for the right current. I'm not sure how practical this would be from a manufacturing cost standpoint but it probably wouldn't be too bad, and it would give you the most precision possible in writing. This would in turn make the reads more reliable, and you possibly wouldn't have to temperature-compensate on the reads.wouldn't the whole chip be about the same temperature, or is that much variance from cell to cell? I don't know -- I offer the 16 segment idea just in case there is enough variation to make a difference. I think it's possible there is.If unwritten cells are at the same state, wouldn't reading their resistance give their temperatures? There's no such thing as an "unwritten" cell. In single-bit mode you have set and reset currents and the resulting resistances, and you can see from the charts that the resulting resistances are dependent on the temperature of the chip at the time of programming. In the multi-bit scheme, you have a multitude of different programming currents and a set of 4 resulting temperature-compensated (or pre-determined) resistances. The dynamic range for OUM is so large that it gives you a huge amount of margin between the 4 levels. As you can see from my picture, the gap between each level is 326%. In actual practice, the dynamic range is going to be smaller, because you have to go by the IR curve for the highest temperature in the specified operating range (say, 80C for commercial applications). But, still, the margin is very generous. 4 levels/2 bits is a gimme, IMO. wily