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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (56033)	9/30/2000 6:23:42 PM
From: Zeev Hed	Read Replies (1) \| Respond to of 93625

Scumbria, I thought you might be referring to the "timing register" on the chip itself. Yes, I agree with you that such registers have been around for quite some times, always as part of a peripheral chip to either the CPU or the memory means, it was never before on the chip of the memory means, by putting it there, one can directly "prep" the processor to know what kind of "packet" to expect next, without having to go through the controller. That is far from obvious. It would have been obvious if there was no performance penalty. But, as you have stated et infinitum, it is a nuisance when you are working with very small packets (pure random access, and you suffer a "latency penalty", less so in SDRAM than RDRAM for various reasons). But it becomes indispensible when you are working with very large data packets (like in streaming video, high end data base management, speech recognition and generation etc.) which are exactly the area where very high frequency processors are supposed to shine. The test for "obviousness" is if a "person trained in the art" would chose this modality, but MU engineers are indeed well trained in the art, and chose to put that register for their EDO DRAM on a separate controller (not because it was not known how to different functions on a single chip, mind you, Trilogy taught us how to do that <G>). Unfortunately, I do not know when the Dramurai finally smarted up and put the register on the DRAM chip itself, but that was too late, if they did it after April 1990. The fact remains that well after that date, "persons trained in the art" (MU's engineers) still preferred to set this function apart of the chip, on a separate memory controller. QED Zeev irrevolute.iuma.com

To: Scumbria who wrote (56033)	9/30/2000 6:24:00 PM
From: mishedlo	Read Replies (2) \| Respond to of 93625

<<The key SDRAM patent covers a "programmable register" for determining memory latency. This is one of the registers found on all SDRAM chips. It has been frequently mentioned in Rambus press releases and conference calls. The programmable register allows the CAS latency to be set by the system it is being used in. This is a useful technique because not all memories sort at the same speed out of the fab. Prior to SDRAM, many EDO systems had a similar register on board the memory controller, which served the same purpose. Since SDRAM is synchronous (has a clock input on the DRAM chips), it was a fairly small logical step to move the same register on board the SDRAM chips. This seems to be what Rambus is claiming as their IP. Had it been known that Rambus wanted royalties for this, none of the DRAM manufacturers would have put the register on board. Instead they would have kept the register in the memory controller and run an extra wire across the interface. This appears to be a submarine patent, and has lots of people very pissed off. If Rambus was smart, they would concentrate on DDR, and lay off the SDRAM claims IMHO.>> Zeev - In Europe does it matter whether or not a patent is a submarine patent or not? Scumbria - If all it takes is to move a wire, why not do it now? And if it was so logical why wasn't it there initially (as implied by your "it was a fairly small logical step to move the same register on board the SDRAM chips", sentence. Finally, RMBS is asking a mere 1% for SDRAM. This is hardly significant to anyone (and do not go into profit margins I know they are low- all they do is raise price a mere 1%). I believe but can not prove, that if the MMs gave into RMBS's demands on DDR initially, and ramped up RDRAM even a little, the SDRAM might not have come up. When someone fights you too hard and tries to steal your IP, maybe you have to ask for more than you deserve just to get what you do deserve. If everyone caves in now, well too late.