Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: John Walliker who wrote (56113)	10/1/2000 5:11:46 PM
From: Dan3	Read Replies (1) \| Respond to of 93625

Re: Kindly give me an example of the use of DDR in memory interfaces from decades ago. The issue I was addressing wasn't DDR in memory interfaces, it was DDR period. And the term I used wasn't DDR in memory, it was DDR. There has been plenty of discussion on this thread of the history of using both edges of a clock. Links to decades old usage of the technology are hard to find because its use pre-dates the internet and so most of the references to it are in print only and not on the web. And that seems to be what Rambus is claiming it owns. The specific confluence of SDRAM, memory, and on die timing registers didn't occur until SDRAM was introduced. Rambus filed for a patent on a memory interface in the early 90's that used a register on the chip to control timing. Several years later, after participating in JEDEC discussions aimed at designing SDRAM, it secretly amended its original application for patents to cover the same use of registers for the different interface that is SDRAM. (almost all patent applications are done in secret - the comment is relevant here because Rambus knew that what it was applying for was already in general use, and Rambus had sat in on meetings where such use was described as public domain and didn't object, implying concurrence) At the time of the first claims, there was extensive discussion of DDR's general use on the this thread. You remember it as well as I do. Dan PS - The 6800 and 6809, like the 6502 series, used a single clock cycle to generate the timing for four internal execution stages by using the rising and falling edges of the base cycle (not just rising edges), and another clock 90 degrees out of phase (giving two rising and two falling edges per cycle) - this allowed instructions to execute in one external 'cycle' rather than four for most CPUs, such as the 8080, which used the external clock directly, so an equivalent instruction would take four cycles, meaning a 2MHz 6809 would be roughly equivalent to a 8MHz 8080. This is different from clock-doubling, which uses a phase-locked-loop to generate a faster internal clock (for the CPU) which is synchronised with an external clock (for the bus). Motorola later produced CPUs in this line with a standard four-cycle clock. The 680x and 650x only accessed memory every other cycle, allowing a peripheral (such as video, or even a second cpu) to access the same memory without conflict. www3.sk.sympatico.ca Clock doubling was old hat by the late 70's. Motorola was already into clock quadrupling.