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To: Paul Engel who wrote (112714)	10/7/2000 1:21:34 AM
From: Joe NYC	Read Replies (1) \| Respond to of 186894

Paul, And how is this little diversion relevant to what you posted when you were "laughing" at me? Except the technicality of saying "data bus" in my post when I should have said "data path"? Joe PS: I don't want to be rude and laugh in your face, but I have to say your post gave me a good chuckle.

To: Paul Engel who wrote (112714)	10/7/2000 11:20:29 AM
From: Scumbria	Read Replies (1) \| Respond to of 186894

Paul, If you feed a 64 bit processor with only 64 bits of data - even at DDR rates of 266 MHz - you will STARVE the processor for memory - greatly limiting performance to that of 32 bit processors. Not true. The L1 and L2 caches on the CPU handle more than 99% of memory accesses, making DDR266 adequate for any CPU we will see in the next few years. Scumbria

To: Paul Engel who wrote (112714)	10/7/2000 3:21:35 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 186894

Paul, <If you feed a 64 bit processor with only 64 bits of data - even at DDR rates of 266 MHz - you will STARVE the processor for memory - greatly limiting performance to that of 32 bit processors.> Oh great. The 460GX chipset for Itanium has a 64-bit FSB. Not only that, but the data transfer rate is 266 MHz (133 MHz double-pumped). So what you're saying is that Itanium/460GX will underperform, right? Paul, for once, I totally disagree with you, and I hope that you're proven wrong! ;-) Tenchusatsu P.S. - In case some of you were wondering, 460GX doesn't use DDR SDRAM. Instead, 460GX uses four PC66 SDRAM channels in parallel to achieve the same bandwidth as DDR SDRAM (coincidentally).