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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: kash johal who wrote (15756)	10/24/2000 2:53:08 PM
From: Daniel Schuh	Read Replies (1) \| Respond to of 275872

Kash, do you think Intel would launch the P4 at 1.2ghz if it were slower that the 1ghz cumine? JC claims to have confirmed some of the rather anemic leaked benchmarks, see jc-news.com Speaking about the Pentium 4, I've finally received confirmation from a trustworthy source that those normalized benchmarks and spec2000 scores are indeed correct (actually, the specfp score was apparently slightly off, but not enough to matter. More info on that will follow, but I have to go to work early in the morning, and it's stupid late right now. Well, Intel can do what it wants, but there might be a problem there. Cheers, Dan.

To: kash johal who wrote (15756)	10/24/2000 3:26:59 PM
From: Dan3	Respond to of 275872

Re: If they actually launch PIV's at 1.2, 1,3 as well as 1.4 and 1.5GHz then i would say intel is in trouble. But if launch starts at 1.4Ghz then converse is true. I think you've got it backwards - there are very strong marketing reasons for Intel to not leave a huge hole between 1GHZ and 1.4GHZ (right where AMD is currently sitting!) so if the launch starts at 1.4GHZ, it would be a very strong indication that P4 IPC is very poor. The ill fated K6-III had superb IPC due to its very low latency cache and short pipeline - the same short pipeline K6-II core w/o low latency cache didn't do nearly as well as the K6-III. But the low latency cache proved to be a clock speed wall the couldn't be breached. The superb IPC let them release this next generation chip at the same clock speed as previous generation chips. Coppermine was the same way - since there was a demonstrable performance improvement even without a big mhz jump, coppermine chips were introduced at pre-coppermine speeds - and were well received. It looks like Intel won't be able to do that with P4. P4 has a 50% lower latency cache than Athlon (and, I think, Coppermine) and, despite this advantage, it evidently still has lower IPC as well. Past history has shown that cache is at least as important a factor in a CPUs scaleability as pipeline length so P4 may hit a speed wall much sooner than many expect due to its cache design. Intel could reduce that risk by increasing the latency of the P4 cache, but then the already poor IPC would likely become intolerable (or else they probably wouldn't have gone with such an aggressive latency out the chute). That very long pipeline may all but shutdown w/o very low latency cache - and very low latency cache has been difficult to scale. Athlon has IPC "headroom" to allow for a pipeline extension if that's needed to permit greater clock speeds. P4 appears to be pushing its limits in cache latency right out of the chute - and the IPC is already non competitive so they can't afford to run with a more manufacturable cache. Just my view on the info that's been released to date, I'd love to hear from someone with real experience in the design of these things. Regards, Dan