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To: kash johal who wrote (15980)10/25/2000 6:47:02 PM
From: pgerassiRead Replies (2) | Respond to of 275872
 
Dear Kash:

You can not tell if, a part was thrown away or not as long as there was no external way of seeing a stepping. If there was, they could have thrown them away because of possible future problems that are acceptable for a top end CPU (like no SMP allowed, etc. that is in the mainstream stepping) or just mixed them in with no one the wiser with some sort of internal remark post sort.

The point is that you assumed that the lower grade is the peak yield speed bin for P4 just because it will be shipped in just two bins 1.4 and 1.5. "cC0" P3 shipped in two bins, 933 and 1000 (per their technical document at that time and any CPUs shipped below that, simply furthers Petz's and my point) just like P4. The latest technical document shows that this stepping now covers down to the bottom of P3 range, and thus now allows or validates the fact that the peak speed bin was below the shipping grades, just like we say P4 will. Its the same situation, and it leads to the same marketing plan. Remember, Intel even had a gap to the lower speeds of 3 grades (866, 900, and 933 were missing when they announced 1000 P3 (AMD announced all the grades in between when, they announced 1G K75). Last time they did it for hype, does not this situation have the same stakes (probably even higher now)?

Yes, being behind drove any real possibility of you being correct down to practically nothing.

Pete

Edit: Check the date of the document you linked to (Oct 2000). Try the previous version say April, May, June, or July. Even someone from Intel stated publically that the 1GHz P3 was from a special production line and not the mainstream (was that from PB, from a designer at the spring IDF, or somewhere else? (I remember reading that somewhere)).