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To: Tony Viola who wrote (115147)10/29/2000 6:45:51 PM
From: Saturn V  Read Replies (1) | Respond to of 186894
 
You are right that ECC may also needed for cache, and you posted a quote saying that Sun forgot to implement ECC on the cache.

I can see designers trying to avoid using ECC for the chip cache. ECC adds silicon real estate, and slows down memory access. A slower cache access on for L1 would dramatically degrade processor performance. ECC on L2 would be more acceptable and makes more sense.

Do you know if ECC is implemented on the L1 or L2 cache from any processor vendor ?

Thanks



To: Tony Viola who wrote (115147)10/29/2000 7:34:30 PM
From: jim kelley  Read Replies (1) | Respond to of 186894
 
A neutron particle most likely won't do anything to an SRAM or DRAM.

But an Alpha particle will wreak holy hell on it.


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