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To: Charles R who wrote (19079)	11/14/2000 5:37:40 PM
From: fyodor_	Read Replies (2) \| Respond to of 275872

<Chuck: My understanding is that all P4 FPU related stuff were being heavily tweaked with SSE2 optimizations for launch.> SSE2 has instructions for double precision FP, as well as some integer SIMD. It does NOT include single precision FP instructions. Many of the common FP benchmarks (e.g. Q3 and SPECfp) are heavily bandwidth limited. The SSE implementation of the P4 may also be better than that of the P3, I don't know (JC might, though). -fyo

To: Charles R who wrote (19079)	11/15/2000 10:22:40 AM
From: jcholewa	Read Replies (2) \| Respond to of 275872

> Note that Quake takes advantage of SSE, not SSE2. Also, specfp's optimizations are mostly or all SSE (prefetch stuff).> > Are you sure? I find it unlikely that P4 FP can outperform P3 unless SSE2 optimizations are in place. > Where do you get this info? My understanding is that all P4 FPU related stuff were being heavily tweaked > with SSE2 optimizations for launch. P4 stands to benefit FAR MORE than PIII with prefetch instructions. The whole point of prefetch is that it leverages memory bandwidth to improve effective memory latency. Da-da, da-daaaaaaa! Pentium 4's platform has far better bandwidth than PIII's platform, so liberal use of prefetch won't choke up P4's memory subsystem like it would on PIII. Add to that the fact that specfp is one of the most memory bandwidth constrained benchmarks out there (slight embellishment). Quake is a similar case, though not quite as extreme.     -JC