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To: fyodor_ who wrote (19163)11/15/2000 3:27:44 PM
From: PetzRead Replies (1) | Respond to of 275872
 
fyo, re your expected order of improved scalability: (P3 SDR, TBird SDR, TBird DDR, Palomino DDR, P4 DDR, P4 Rambus), the evidence is that TBird DDR is way ahead of P4 Rambus (see Message 14812122 )

The problem with P4 Rambus vs. TBird DDR is
P4 is worse than TBird (even more so, Palomino) for two reasons:
1. Small D-cache causes applications to be limited by memory latency as L2 can't fill all the requests demanded of it
2. Branch mispredicts aften cause a delay proportional to memory latency rather than to clock speed

Rambus systems are worse than DDR systems because of the same memory latency problems.

Petz