Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: pgerassi who wrote (21806)	12/7/2000 1:53:26 PM
From: Pravin Kamdar	Respond to of 275872

Pete & Young Watson, Regarding SOI fabrication: sysopt.earthweb.com Pravin

To: pgerassi who wrote (21806)	12/7/2000 6:38:44 PM
From: fyodor_	Respond to of 275872

pgerassi: If the chips are limited by how much heat they dissipate, reducing the amount of power used and thus, heat generated, the logic can then run faster. Even for transistors that are not limited by heat dissipation, lowering the capacitance will increase the switching speed (since switching speed is inversely proportional to the capacitance). -fyo

To: pgerassi who wrote (21806)	12/7/2000 9:21:59 PM
From: THE WATSONYOUTH	Read Replies (3) \| Respond to of 275872

SOI places the active regions of a chip in tubs of SiO2. This reduces the parasitic capacitance and substrate leakage that occurs. Both contribute to a lowering of the power required for CMOS logic circuits. Using a low-K dielectric for these tubs would reduce even further the power required. Substrate leakage has no effect on active power. It has only a very small effect even on standby power which is dominated by device off current (not area junction leakage). The impact of area junction capacitance diminishes rapidly with scaling. It will decrease as the square of the scaling factor while perimeter and gate capacitance decreases linearly. Thus, at .13um and below, area capacitance will be of ever decreasing importance. In addition, Intel has done a remarkable job of engineering their junction and well doping profiles to minimize area junction capacitance. This, to my knowledge, has not been matched by competitors. Also, most advanced processor circuits are dominated by wiring capacitance rather than junction capacitance. (note the need for low K dielectric) For a heavily wire loaded circuit, the % junction capacitance load is probably less than 5%. Another feature of SOI which needs to be accounted for is the memory effect. Since the body of the device is floating, it will be at various potentials depending on the switching history of that device. This causes a delay uncertainty which must be accounted for thus introducing a history effect guard band into circuit design. It can be as large as 5% of the actual delay and it increases as Vdd decreases. This comes right out of whatever performance gain is claimed. When these issues are taken into account, in my opinion, you will see no more than 10% to perhaps 15% performance gain due to SOI over the best bulk process. This is about half of what is claimed by IBM and others. And, as I've pointed out before, you only realize this gain if the SOI process(at fixed channel length) is ready at the SAME time as the equivalent bulk process (at the same channel length) If it is delayed 6 months or more relative to the bulk process, the advantage is largely lost. There are already indications that AMD's .13um process might be 6 months or more behind Intel. What if it is 9 months?? or 12 months??? I hope AMD realizes what they are getting into with SOI. There are many many more issues beyond just performance and all can contribute to delays. I would have liked to have seen concurrent development of bulk and SOI processes for .13um. Perhaps that is what they really are doing. We'll see soon enough. THE WATSONYOUTH