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To: Elmer who wrote (125683)1/20/2001 11:51:31 PM
From: Joe NYC  Read Replies (1) | Respond to of 186894
 
Elmer,

When is the spring Intel developers conference? Maybe Intel will reveal some details there.

Joe



To: Elmer who wrote (125683)1/22/2001 2:18:36 AM
From: jcholewa  Read Replies (2) | Respond to of 186894
 
> But you think it probably won't happen? It's not impossible
> but with Intel pushing the P4 so much stronger nowadays, maybe it won't.

I've always considered it only a distant possibility. I don't think I've actually ever seen it on any of Intel's roadmaps. I mean, DDR SDRAM (for example) was even listed on the roadmaps months before Intel committed to it (it was originally listed as POR -- "Per OEM Request"). So I would have expected to see such a 200MHz creature at least provisionally there.

When P4 reaches 130nm, it will become Intel's high end cpu for PCs. The P6 family will be (probably) relegated to "Celeron" status (or some equivalent lower end), imho. Intel just made the jump to 100MHz chipset-to-cpu clock for their low end products, and I would imagine that they would see a jump to 133MHz end of 2001 or beginning of 2002 as a natural progression. Is it worth it to try to double that chipset-to-cpu bandwidth for a processor which might not even last too far beyond that (I have no idea how long it'd last, but P4 at 130nm should be smaller than the first well-received Celeron [Mendocino, which I recall was 155sqmm or so])?

By the way, do you see it as a possibility that Intel might lower the size of the cache (to 128KB, for instance) of the P4 when they adapt it to the "Celeron" end of the market? At 130nm, the die savings would not be too huge, but it'd be greater than zero.

    -JC