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To: Elmer who wrote (126043)1/25/2001 11:55:24 PM
From: Joe NYC  Read Replies (1) | Respond to of 186894
 
Elmer,

I remind our AMDite friends that Intel has never shipped a P6 generation chipset die that wasn't SMP capable.

They had to wait to P7 generation chipset to get to sorry state of no SMP that AMD is in. If you were a betting man, who would you bet on as far as being first to deliver SMP for the 7th generation processors?

Joe



To: Elmer who wrote (126043)1/26/2001 1:08:21 AM
From: Paul Engel  Read Replies (2) | Respond to of 186894
 
ELmer - Re: "AMD has a long history of failure and zero (successful)experience in debugging SMP architectures, and they expect to convince customers that they will have a totally new SMP architecture ready for Sludgepumper running on an unavailable 64bit operating system? Now that's what I call an uphill battle! "

Amen, brother !

By the way - what Motherboard are you using for your dual Celeron system?

Paul



To: Elmer who wrote (126043)1/26/2001 9:40:07 AM
From: EricRR  Read Replies (1) | Respond to of 186894
 
AMD is finally coming to grips with the realization that the EV6 bus is a total disaster and they are throwing in the towel

A pain in SMP does not imply a "total disaster." EV6 is a perfect match for DDR.

BTW- Any guess as to when will we see the first 0.13 P3 in a notebook? CSFB says October (but maybe that was for desktops)