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To: Paul Engel who wrote (126599)	2/4/2001 12:43:45 PM
From: Tony Viola	Read Replies (4) \| Respond to of 186894

Paul, >Here is what VIA has said about AMD's SMP Server effort: "Unlike the MP Pentium chipsets VIA makes, making an AMD MP chipset is a bit more difficult... ...We frankly expect AMD to meet with some success with their MP chipset. Still, we're not sure whether they will meet with enough success to convince VIA to develop their own solution. Only time will tell." Good, frank article on VIA's opinion. Point is, even if VIA does a chipset around AMD's "server effort", it doesn't mean the likes of Compaq, HP or IBM will touch it. Those guys want complete sever product lines up to 8-way and beyond. Maybe the likes of TigerDirect, Everex and Accubyte will use them. Like, who cares. Tony

To: Paul Engel who wrote (126599)	2/4/2001 3:52:48 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 186894

Paul, from your Sharky quote: <So in order to make an MP Athlon chipset, AMD had to put two EV6 busses. This increases the chipset die size and pin count, which thereby increases the chipset's cost. AMD has a shared bus architecture relying on LDT planned for their K8 series processors.> Sharky is right in that multiprocessor Athlon chipsets require a separate EV6 interface for each processor, which complicates chipset design. However, Sharky is wrong in saying that LDT is a "shared bus architecture." LDT is actually going to be a "switched fabric" architecture, which is going to be the wave of future SHV servers, frankly speaking. Each LDT connection is point-to-point, like EV6, but LDT is more sophisticated and has a higher bandwidth-per-pin, which allows for fewer pins. Of course, just because AMD has nice LDT foils doesn't mean they'll execute flawlessly on the technology. Based on the numerous server delays we've seen from Sun, Alpha, AMD, and of course Intel, I have to wonder whether AMD has what it takes to drive LDT into high-end servers. Tenchusatsu