Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (27483)	2/5/2001 5:53:56 PM
From: Scumbria	Read Replies (2) \| Respond to of 275872

John, Dirk Meyer produced a very well balanced design on the first pass. Scumbria

To: Petz who wrote (27483)	2/5/2001 6:57:31 PM
From: kapkan4u	Read Replies (1) \| Respond to of 275872

<Their biggest problem was vastly underestimating the die size> From what I heard, the negative effects of the P4's hyper pipeline on IPC were simulated too optimistically until the summer of 1998. The actual silicon turned out to be yet even worse for branch mispredicts and trace cache misses. Kap

To: Petz who wrote (27483)	2/5/2001 9:38:45 PM
From: THE WATSONYOUTH	Read Replies (2) \| Respond to of 275872

Their biggest problem was vastly underestimating the die size, which resulted in dropping execution units, cache sizes and decoding ability. It is possible that Intel was severely back end limited with the P4 design at .18um with only 6 levels of Al. If you recall, they had to go thru an extensive hand layout of all the back end levels so as not to be back end limited with 6 levels of Al on the P3 design at around 1 GHz. They had no other choice since they didn't want to move to Cu BEOL until .13um. I speculate that P4 was never intended (at least in the 1.5GHz-1.7GHz regime) to be released at .18um in Al. Again, they had no choice but to release it when their 1.13GHz P3 backfired and AMD pushed Athlon to 1.2GHz at .18um. This might explain the huge die size. I could never rationalize 217mm2 for 42 million devices when P3 was less than 100mm2 for 28 million. If they were severely BEOL limited at 1.5GHz to 1.7GHz because of the .18um Al, that might explain the extremely large die size. We might get a clue when P4 moves to .13um. all speculation THE WATSONYOUTH P.S. It's getting serious here in N.Y. with about 14 inches of snow all ready today and perhaps a few more on the way.