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To: Dan3 who wrote (126947)	2/8/2001 3:35:09 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 186894

Dan, <the 128 byte wide cacheline of P4 clears 128 bytes of the cache if even a one byte boolean value is read from memory.> Ever hear of temporal and spacial locality? Usually when you access a variable within a large cacheline, the other variables you need in the near future are also located in the same cacheline. <I think you have provided an excellent explanation for some of P4's observed thirst for bandwidth.> Any processor with a super-long pipeline running at high speeds will thirst for bandwidth, no matter what the length of the cacheline is. Tenchusatsu

To: Dan3 who wrote (126947)	2/9/2001 12:31:57 AM
From: Paul Engel	Read Replies (3) \| Respond to of 186894

Blow Hard Dan - You'll love this little RAMBUS story !!! Looks like the Pentium 4 production levels are taking off ! Toshiba, NEC to boost production of Rambus memory By Bloomberg News February 8, 2001, 3:50 p.m. PT news.cnet.com tag=prntfr TOKYO--Toshiba and NEC plan to increase the number of high-speed computer memory chips they produce to meet an expected rise in demand, Tokyo's Nikkei English News said, citing unidentified industry sources. Toshiba is to raise production of Dynamic Random Access Memory (DRAM) based on Rambus designs to 8 million a month from 2.3 million in September, NEN said. The Rambus chips, which can transfer data at twice the speed of standard DRAM, is to comprise 60 percent of Toshiba's total production, NEN said. NEC is to increase monthly production to 5 million chips from 2 million in September, NEN said. Both companies plan to cut production of lower-grade chips due to lower demand. Demand for the faster chips is expected to grow as Intel looks for chips for its Pentium 4 processor.