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To: Charles R who wrote (28720)	2/15/2001 10:24:20 PM
From: Scumbria	Respond to of 275872

Chuck, In the last 6 years we have been through ED0, SDRAM, RDRAM, and now DDR- with many speed grades in between. Soon we will have the 4 bank version of RDRAM too. I have seen lots of processors die because of integrated memory controllers, and only one prosper (briefly.) The CPU bus should be as clean and simple as possible. It is analagous to an API in the software world. You should be able to plug any kind of DRAM into any CPU, with the correct driver (i.e. the external memory controller.) You should even be able to plug RDRAM into an Athlon box, in case some moron wanted to use it. Scumbria

To: Charles R who wrote (28720)	2/15/2001 11:56:21 PM
From: Joe NYC	Read Replies (2) \| Respond to of 275872

Chuck, I would come to the exactly opposite conclusion. i.e., integrated DRAM controller IMPROVES* time to market. No need to keep getting stuck with the same old motherboard signal integrity problems.* I agree. I pointed out how long, and how many steps it took us to get even the PC-133 interface for Tbird with somewhat reasonable performance - from May 2000 to February 2001, with release of KT-133A. The processors already have an "entrance" through which data gets to the CPU, and it is the FSB. We are still mired in one transition from 100 MHz to 133 MHz FSB, and the next transition to 166 MHz FSB is innevitable, which will require possibly another spin of the CPU. Even when we are done with this spin, which will give use 133 or 166 MHz FSB, at this time, this just leads to the "middleman", the northbridge, so it takes 2 changes to take advantage of it instad of 1: on the CPU side and on the Northbridge side. As we witnessed, there are huge delays in getting both of them to market and on the motherboards. And even when we are done, we still end up with a solution that is wasting cycles of passing data between number of interfaces: From DRAM to the northbridge, from northbridge to the its EV6 bus interface, from there through the traces to the EV6 bus interface on the CPU, and ultimately to the CPU core. Considering how critical memory latency is to the ultimate performance of the CPU, this may be wasting 1 to 2 speed grades worth of performance. Another way to look at it is from resource utilization point of view. If AMD designs and implements memory controller in the northbridge, AMD will not have to design a standalone Northbridge, neither will Via, Ali, Sis, Micron, Nvdia, API, Serverworks or anyone else. They can dedicate the saved resources to addressing other bottlenecks, interfaces to other I/O devices, or other infrastructure needs. Right now, what we have is almost $200 high end motherboards, where Northbridge is really the center of the motherboard, it has it's own heatsink and fan, and huge number of traces going in all directions, with all kinds of signal integrity issues to deal with (as you mentioned). Going to integrated controller may cut the cost of the same high end motherboard maybe all the way down to $100, which is huge. Anyway, we have this supposedly flexible platform of separate CPU and Northbridge, and 3 months after introduction of 133 MHz FSB CPUs and 3 months after introduction of 760 chipset, we are only this month beginning to see first motherboards and systems, and this is not even a new CPU. Joe