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To: Paul Engel who wrote (30404)3/6/2001 8:33:26 AM
From: Dan3Read Replies (3) | Respond to of 275872
 
Re: the largest useable L2 cache just happens to be the largest L2 cache on a currently available AMD CPU !!!!

Only for servers. The ironic thing is that Intel's design, which has lower latency, but is "shallower" due to its lower associativity, is better suited to single user desktops, yet is the only X86 cache design presently available for servers. AMD's cache design, with it's higher latency limiting performance in single user configurations, but better suited for the many active processes usually seen only in servers due to its depth, is available only in desktops.

P4 is a pure desktop design, and Foster is going to have a hard time in a many process environment. A process that "wakes up", loads its registers to check something, then releases control of the CPU to give it to the next scheduled process, is much more likely to use hundreds of cycles as it reads from main memory than the same process would on an Athlon core which is capable of maintaining nearly twice as many threads in its cache. Merced was supposed to be the server chip, and supposed to be ready 3 years ago - since then it's been a salvage operation. McKinley's release date will be getting close to the 4th year of rework after the expected initial release date.

Hope springs eternal in the IA-64 fan's heart, but so far, not so good.

Dan