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To: Scumbria who wrote (30865)3/8/2001 6:37:36 PM
From: fyodor_Read Replies (1) | Respond to of 275872
 
Scumbria: They don't have any choice. It would be smarter for them to make the cache larger, and add a cycle latency, but the damage is irreparable at this point.

The engineering argument might have been that they could save a cycle on the latency by foregoing FPU accesses to the L1 cache. Supposedly, most floating point apps wouldn't suffer much as there are generally fewer branches and greater parallellity.

-fyo


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