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To: Petz who wrote (33375)	3/25/2001 12:42:00 PM
From: fyodor_	Respond to of 275872

Petz: 1. I don't believe the 200 ms. switching time and suspect it's 200 microseconds. Someone might have used "ms" as an incorrect abbreviation and I wouldn't trust any marketing types to know the difference. That could well be. I haven't been able to find any specific numbers on the switching time in the tech docs. 2. Additional MHz rates may be obtained by rapidly switching the divider. LIke "divide by 10 for 16 cycles then divide by 11 for 32 cycles." Just about any average clock cycles per second could be obtained and the power consumption would be proprotional to the average frequency. NO! This is not possible. At least not with PowerNow! mk1. Every time the processor switches operating frequency, the pipeline is completely flushed. See my post to Joe for details: Message 15559323 3. As an alternative to (2), if the CPU is switching randomly dozens of times a second, then the frequency displayed by an LED averaging over, say 1/10 second, could be displaying just about anything. This is more probable, imho. -fyo

To: Petz who wrote (33375)	3/25/2001 12:55:23 PM
From: Pravin Kamdar	Respond to of 275872

John, 1. I don't believe the 200 ms. switching time and suspect it's 200 microseconds. You could be right, but I suspect that the large signal changes that take place during PowerNow! adjustments probably need the 200ms to settle out. Pravin.

To: Petz who wrote (33375)	3/25/2001 7:54:47 PM
From: TechieGuy-alt	Respond to of 275872

I don't believe the 200 ms. switching time and suspect it's 200 microseconds. Someone might have used "ms" as an incorrect abbreviation and I wouldn't trust any marketing types to know the difference. I've been working with an embedded CPU from AMD- the AMD ELAN SC520. To give you a reference, you can change the operating freq of this cpu by writing to a register from 133 to 100Mhz (and back). The CPU reference guide says that the PLL needs upto 1ms to change the clock. (and there is no need to flush any cache too). As another reference, I've worked on a embedded Toshiba CPU (the TLC900 series) that has a similar clock changing scheme that we used (though not a PLL, just dividers). This CPU not only has various clock "gears" (as they called them), but actually 2 separate clocks. One high MHz (upto 20MHz) and another 32KHz for ultra low power. Again just for reference, we could start the 32KHz clock crystal from the OFF mode to "stable" mode in 10ms. Note that this was starting the oscillation, not changing the multiplier of a PLL, which would happen much quicker (IMHO). Hence, any figure below 10ms is most likely (and usable). 200ms for dynamic clock adjustment is quite worthless, as you would drop DVD frames out of the wazoo if it took that long. JMHO TG