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To: Scumbria who wrote (33476)	3/26/2001 8:28:51 AM
From: fyodor_	Read Replies (1) \| Respond to of 275872

Scumbria: but the small single ported P4 cache is inadequate to support one thread, much less multiple threads. If someone could explain this in a bit more detail for me, I'd be quite grateful ;) Oh, one more thing about the Athlon from the same Ace's article I referenced earlier: Page 105 in the Athlon optimization guide reads: "Loads and stores are scheduled by the AMD Athlon processor to access the data cache in program order." and citing Andreas Kaiser: For loads and stores, the K7 has 2 queues, a 12-entry LS1 and a 32-entry LS2. Load/store-ops are dispatched to LS1 and removed in-order two at a time when the addresses are available (stores and load misses are moved to LS2). So if the oldest op in LS1 does not have its address available, then LS1 stalls. This in-order nature of LS1 allows load-load reordering only for L1 cache misses. -fyo

To: Scumbria who wrote (33476)	3/26/2001 9:55:31 AM
From: bacchus_ii	Read Replies (1) \| Respond to of 275872

RE:"the small single ported P4 cache is inadequate to support one thread, much less multiple threads." For me the big question is how the trace cache will be managed in multiple threads. Will they split the cache in as many sections as there are threads? Will they let the trace cache being polluted by others threads inserted instructions? Frankly, in multiple threads mode, I don't understand anymore the usefulness of the trace cache at all. Gottfried