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To: dale_laroy who wrote (33842)3/27/2001 9:58:28 PM
From: porn_start878Read Replies (3) | Respond to of 275872
 
What I knew is AMD was dropping EV6, and was to use LDT for chipset to chispet connections, the whole net being build as a NUMA architecture. I haven't read nowhere they were to use it for NB to PCI and/or NB to AGP (what would the the use for it? PCI and AGP wouldn't benefit from the higher bandwidth unless we move to new standards and AMD specified that LDT was for chip to chip connections, and wasn't to replace PCI standard and even less AGP standard)

The only advantage I see could barely be design simplification, as PCI and AGP signals can be carried in much less pins if transfered via a LDT hub... but it seems very unlikely.

So if NUMA is in the chipsets to unify memory in multiple CPU config, LDT is between them to cary info, then we come back to my original question : Of what kind will be the memory bus, and will it cope with the impreesive i850 performance at, say 533MHz?

Max



To: dale_laroy who wrote (33842)3/27/2001 10:53:33 PM
From: Joe NYCRespond to of 275872
 
dale,

EV6 dies with Athlon/Duron.

Athlon definitely and Duron probably will be with us as marketing names for a long time. I wonder if AMD will come out with a new marketing name for x86-64 enabled CPUs or for their server CPUs.

EV6 will definitely live in Palomino, and we will see about Tbred series, if AMD retains the bus, or switch all of the processors to LDT.

Joe