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To: fyodor_ who wrote (35565)4/12/2001 1:16:32 PM
From: PetzRead Replies (1) | Respond to of 275872
 
My original post was not very clear, let me restate it with the changed parts in bold:
The extra die space to continue to support regular DDR along with DDR-II is probably insignificant. In fact there is no reason that an integrated northbridge could not continue to support straight DDR as well as DDR-II by sharing the same I/O pins and having a control bit to change the interface. The problem will be getting DDR-II right the first time, but if the DDR-II interface proved buggy, at least these chips could still support DDR.

BTW, I noticed something new on my 1.33 AXIA -- the motherboard reports on the microcode download level on the bootup screen. AMD must have increased the re-programmability of the microcode on the AXIA stepping.

Returning to the original integrated Northbridge idea, is there a way to make most of the northbridge section a field programmable gate array which is programmed after the rest of the die has been manufactured?


You responded:
Sure, you could leave much of the timing up to later "programming", but the interface itself would have to be hard-wired in silicon.

FPGA's in their various forms are just a bunch of gates and sometimes memory cells which can be programmed electrically to implement just about anything. Some use internal flash memory, some use fuses which are blown. What I'm not sure of is whether
1) Doing it this way would lower performance, for example, make CAS 2 or CAS 2.5 impossible or FSB speed > 133 MHz impossible?
2) Would vastly increase production costs, e.g., require 3 additional layers?
3) Is incompatible with AMD process technology?

Petz